Programming the FPGA
The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in VHDL. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
The DAC
Interface
The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal. A serial communication transfers one 19-bit word:
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- A(4:0) is a 5-bit address to select the target DAC channel. A4 is the most-significant bit and transfers first.
- DB(13:0) is a 14-bit voltage code, where .
- DB = 0 yields .
- DB = (full scale) yields .
The three lines of the interface are SYNC, SCLK, and D_in. A write to the DAC begins with a falling edge of SYNC. The next 19 bits (counted off by SCLK) are saved into a shift register The next transfer begins on another falling edge of SYNC, but transfers do not overlap or interrupt. A minimum of 200ns is required between exchanges. SCLK is ignored except during the 19 shift cycles. The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically. In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz. For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
