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| | * [[Programming the temperature sensor]] | | * [[Programming the temperature sensor]] |
| | * [[Programming the ADC]] | | * [[Programming the ADC]] |
| − | | + | * [[Programming the Ethernet controller]] |
| − | == The ADC ==
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| − | | |
| − | The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip here].
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| − | === Interface (A) ===
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| − | | |
| − | The AD7928 ADC has several features that we do not need: the shadow/sequencer and the multiple power modes. They could be useful for more advanced or efficient functioning of the system, but are not needed. Thus we will simplify the interface by turning these features off and running the ADC is the most basic mode.
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| − | | |
| − | The ADC has a four-wire interface that is compatible with the SPI bus protocol. The four lines are:
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| − | * ''/CS'': Active-low chip select. This line is high when the ADC is idle and goes low for 16 cycles during a conversation. As this is active-low and the only other chip on the bus (the temperature sensor) has an active-high chip select line, it is possible to use a single chip select. That would cause one or the other chip to always be running, which would be more information than we need or than we can send across Ethernet, but it is a possible design decision.
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| − | * ''SCLK'': A serial clock.
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| − | * ''D_out'': Serial data out line, for communications from the ADC to the FPGA. This line idles in high-Z.
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| − | * ''D_in'': Serial data in line, for communications from the FPGA to the ADC.
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| − | | |
| − | On startup the ADC requires two "dummy" conversation that write all ones to the ADC and read garbage data from the ADC.
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| − | | |
| − | A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC. The 12-bit control register has the following format:
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| − | | |
| − | {| align="center" cellpadding="1" border="1" cellspacing="1"
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| − | |
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| − | {| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
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| − | |- style="font-size:smaller; height:10px"
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| − | | style="width:8.33%" |11 || style="width:8.33%" |10 || style="width:8.33%" |09 || style="width:8.33%" |08 || style="width:8.33%" |07 || style="width:8.33%" |06 || style="width:8.33%" |05 || style="width:8.33%" |04 || style="width:8.33%" |03 || style="width:8.33%" |02 || style="width:8.33%" |01 || style="width:8.33%" |00
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| − | |-
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| − | | Write || Seq || DC || Addr<sub>2</sub> || Addr<sub>1</sub> || Addr<sub>0</sub> || Pow<sub>1</sub> || Pow<sub>0</sub> || Shadow || DC || Range || Coding
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| − | |}
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| − | |}
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| − | | |
| − | The sections of the control register are:
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| − | * Write:
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| − | ** if 0, do not update the remaining 11 bits of the control register
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| − | ** if 1, write new data to the control register
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| − | * Seq: used for a feature we don't need: set to zero
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| − | * DC: don't care
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| − | * Addr(2:0): 3-bit address of channel to report on during next conversation
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| − | * Pow(1:0): used for changing power modes: set to "11"
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| − | * Shadow: used for a feature we don't need: set to zero
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| − | * DC: don't care | |
| − | * Range: set to zero
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| − | ** if 0, analog input range is 0 to 2*V<sub>Ref</sub>
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| − | ** if 1, analog input range is 0 to V<sub>Reg</sub>
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| − | * Coding: set to zero
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| − | ** if 0, output is twos-complement
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| − | ** if 1, output is binary-coded decimal
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| − | | |
| − | Thus a conversation to read the voltage only (and not update the control register would look like
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| − | {| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
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| − | | style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X
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| − | |}
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| − | and a conversation to set up a read on channel A(2:0) would look like
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| − | {| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
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| − | | style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
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| − | |}
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| − | where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved. The don't-care states in bits 9 and 2 we can set to zero.
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| − | | |
| − | The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation. We are going to use twos-complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.
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| − | | |
| − | The control interface to the FPGA core will be:
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| − | * ''Clk'': input: Clock line
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| − | * ''Rst'': input: Asynchronous, active-low reset line
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| − | * ''Go'': input: Pulse to begin transmission
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| − | * ''Wr'': input: Flag whether or not to write new data to control register
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| − | * ''A(2:0)'': input: Address to write to control register
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| − | * ''C(2:0)'': output: Address of data coming from ADC
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| − | * ''D(11:0)'': output: Data from ADC
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| − | * ''Done'': output: Flag to tell core that new data is ready
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| − | | |
| − | === Emulator (A) ===
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| − | | |
| − | [[Image:ADC Emulator Block.JPG|thumb|ADC emulator functional block diagram]] | |
| − | | |
| − | The functional block diagram for the emulator is shown to the right. The blocks are:
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| − | * '''shift in 16'''
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| − | ** This block is a 16-bit shift-in register with asynchronous, active-low reset and shift enable. Custom outputs select the write bit and the data bits from the input string. This register is designed to shift all 16 cycles of a transfer, but only make use of the first 12 bits of the input.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''Rst'': asynchronous, active-low reset
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| − | *** ''En'': shift enable
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| − | *** ''D'': data in line
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| − | ** outputs
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| − | *** ''Q_W'': the write bit from the input string
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| − | *** ''Q_D'': the 11 data bits from the input string
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| − | * '''control reg'''
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| − | ** This block is an 11-bit register with asynchronous, active-low reset and a clock enable line.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''Rst'': asynchronous, active-low reset
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| − | *** ''En'': read enable
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| − | *** ''D'': data in
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| − | ** outputs
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| − | *** ''Q'': data out
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| − | * '''3-to-8 demux'''
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| − | ** This block is a 3-to-8 demultiplexer.
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| − | ** inputs
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| − | *** ''D'': data to be demuxed
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| − | *** ''S'': 3-bit select
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| − | ** outputs
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| − | *** ''Q'': 8-bit output
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| − | * '''error flag'''
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| − | ** This block generates a flag to ensure that data in the control register is in the right format (to help verify synchronization). The format is: d00ddd110000, where a "d" is a don't-care state (0 or 1).
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| − | ** inputs
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| − | *** ''D'': data in
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| − | ** outputs
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| − | *** ''Err'': active-high error flag
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| − | * '''shift out 15'''
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| − | ** This block is a 15-bit shift-out register with asynchronous, active-low reset and a shift/load toggle. Custom inputs load the address (MSB first) as the first 3 bits and the data as the last 12 bits. Idle output is a zero.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''Rst'': asynchronous, active-low reset
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| − | *** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
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| − | *** ''D'': data in
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| − | *** ''A'': address in
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| − | ** outputs
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| − | *** ''Q'': data out
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| − | | |
| − | === Controller (A) ===
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| − | | |
| − | [[Image:ADC Controller Block.JPG|thumb|ADC controller functional block diagram]]
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| − | | |
| − | The functional block diagram for the controller is shown to the right. The blocks are:
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| − | * '''counter'''
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| − | ** This block is a 5-bit counter. It counts out 17 cycles: from the idle state, a pulse on the Go line begins a count of 16 cycles (during which time CS is low), then on the 17th cycle re-enters the idle state to await another pulse on Go. The Go line is ignored during a 17-cycle run.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''Rst'': asynchronous, active-low reset
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| − | *** ''Go'': pulse to leave idle state
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| − | ** outputs
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| − | *** ''CS'': active-low chip select
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| − | * '''delayer'''
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| − | ** This block is a single-cycle signal delayer.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''D'': signal to be delayed
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| − | ** outputs
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| − | *** ''Q'': delayed signal
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| − | * '''shift out 12'''
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| − | ** This block is a 12-bit shift-out register with asynchronous, active-low reset and a shift/load toggle. Custom inputs load the write bit and address bits, then fill in the remaining bits (W00AAA110000). The register drags a trailing zero. The output idles at zero when output is not enabled.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''Rst'': asynchronous, active-low reset
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| − | *** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
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| − | *** ''D_W'': write bit input
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| − | *** ''D_A'': address bits input
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| − | ** outputs
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| − | *** ''Q'': serial output
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| − | * '''shift in 15'''
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| − | ** This block is a 15-bit shift-in register with asynchronous, active-low reset and shift enable. Custom outputs select the address bits and data bits.
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| − | ** inputs
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| − | *** ''CLK'': clock
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| − | *** ''Rst'': asynchronous, active-low reset
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| − | *** ''Sh'': shift enable
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| − | *** ''D'': data in
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| − | ** outputs
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| − | *** ''A'': address out
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| − | *** ''Q'': data out
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| | | | |
| | == Ethernet controller == | | == Ethernet controller == |
The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in VHDL. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
Open questions
Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
- What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
- Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component. This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.
- Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
- The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
Component code
Ethernet controller
Interface (E)
- See also: Ethernet packets
Emulator (E)
Controller (E)
Reset and Initialization
On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to reset the system on a command from the PC.
The DAC
The AD5535 DAC has an active-low reset pin. Pulling that pin low will reset the DAC, zeroing all channels.
The temperature sensor
The AD7314 temperature sensor does not have a reset function. It self-initializes on powering up.
The ADC
The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up. The reset procedure is to hold the Din line high while performing two dummy conversions. During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA. It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.
The Ethernet controller
The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization"). The main points of the process will be covered here.
- The first step is to wait for the reset pin to rise. No flag will be raised upon the completion of this step other than the reset pin (which is an input to the CP2200/1) being high.
- The second step is to wait for Oscillator Initialization to complete. Completion of this will be signaled by an interrupt request signal.
- The third step is to wait for Self Initialization to complete. Completion of this will also be signaled by an interrupt request signal.
- At this point all interrupts will be enabled. Any interrupts which the FPGA will not handle should be disabled now.
- The physical layer must be initialized, which is itself a multi-step process.
- See section 15.7 "Initializing the Physical Layer"
- If auto-negotiation is to be used see section 15.2 "Auto-Negotiation Synchronization."
- Enable the Link, Act, or Activity/Link LED(s).
- The MAC must now be initialized, another multi-step subprocess.
- See section 14.1 "Initializing the MAC."
- The receive filter must now be configured.
- See section 12.4 "Initializing the Receive Buffer, Filter and Hash Table."
- The CP2200/1 is now ready for regular operation.
This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing the board and the PC are unable to communicate.
