Difference between revisions of "FPGA Programmer"

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== (110) Program DAC ==
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== (110) DAC Programmer ==
  
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This block will have a substate to obtain the programming mask.  It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask.  It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet.  Then it transitions to state 111.
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The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values.
  
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inputs
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The mask selects which channels must be altered. Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 0  and the LSB of the fourth byte will be channel 31.  Thus, if only channels 5 through 17 are to be programmed, the mask would contain:
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* ''Clk'': clock
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{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
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* ''/Rst'': asynchronous, active-low reset
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! First data byte
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* ''State'': 3-bit state value
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| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1
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|-
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! Second data byte
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| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1
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|-
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! Third data byte
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| 1 || 1 || 0 || 0 || 0 || 0 || 0 || 0
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|-
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! Fourth data byte
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| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0
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|}
  
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internal signals
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== Programming Details ==
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* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
 
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* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
 
  
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blocks
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[[Image:P-packetPayload.png|frame|P-packet Format]]
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* '''Mask Fetcher'''
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** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
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** inputs
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The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. The first stage involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows immediately after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the [[Programming_the_DAC|DAC Controller]] for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered the mask must contain 0's for the corresponding bits. If a requested value exceeds the voltage level hardwired into the FPGA firmware, this maximum value is set instead of that requested by in the P-packet. The responding D-packet will reflect this correction.
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*** ''Clk'': clock
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*** ''/Rst'': asynchronous, active-low reset
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The [[FPGA_Registers#DAC Register|DAC Register]] is pulsed simultaneously with the DAC controller to record the programmed value. These will later be sent back to the PC for confirmation. (No feedback from the DAC chip itself is possible. Channel 31 is reserved for calibration and is connected to ADC channel 7.) Because the combined duration of these operations exceeds the reception time of the minimum-length packet, the module inhibits the Receiver Interface of the Ethernet Controller for the duration of the programming to prevent incoming packet pileup and receive buffer overload.
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*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
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*** ''TxRx_D'': 8-bit data bus from transceiver
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*** ''TxRx_Done'': ''Done'' signal from transceiver
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=== Ports ===
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** outputs
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*** ''TxRx_Go'': ''Go'' input on transceiver
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* ''Clk'': [in] clock
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*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
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* ''Rst'': [in] asynchronous reset
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*** ''TxRx_A'': ''A_in'' bus on transceiver
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*** ''Mask'': 32/24/16-bit readout of programming mask
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*** ''Done'': pulse to signal that mask has been obtained
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Write signals to the [[Programming_the_DAC|DAC Controller]] and [[FPGA_Registers#DAC Register|DAC Register]]
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* '''Programmer'''
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* ''DAC_iGo'': [out] active-low "Go" signal
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** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0.  Also writes the value to the internal DAC value storage registers (or Flash memory or other).
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* ''DACReg_En'': Enable (write) signal to DAC Register
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** inputs
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* ''DAC_Addr'': [out] 5-bit DAC channel address
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*** ''Clk'': clock
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* ''DAC_D'': [out] 14-bit voltage value for the register and DAC Controller
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*** ''/Rst'': asynchronous, active-low reset
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* ''DAC_Done'': [in] "Done programming" signal from DAC controller
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*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
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*** ''TxRx_D'': ''D_out'' bus on transceiver
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*** ''TxRx_Done'': ''Done'' signal on transceiver
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[[FPGA_Registers#State_Register|State Register]] Control Lines
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** outputs
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* ''state_En'': [out] state register enable (write) signal
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*** - DAC control lines -
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* ''state_D'': [out] (3-bit) state register input
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*** ''TxRx_Go'': ''Go'' signal on transceiver
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* ''state_Q'': [in] (3-bit) state register output
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*** ''TxRx_R/W'': ''R/W'' signal on transceiver
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*** ''TxRx_A'': ''A_in'' bus on transceiver
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*** ''Sel'': 5/5/4-bit select bus to internal registers
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[[FPGA_Transceiver|Transceiver]] Control Lines
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*** ''Data'': 32/24/16-bit data bus to internal registers
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* ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte
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*** ''Done'': pulse to signal completion
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* ''TxRx_RiW'': [out] active-high read, active-low write flag
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* '''Discarder'''
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* ''TxRx_Aout'': [out] EC control register address (8-bit)
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** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
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* ''TxRx_Din'': [in] EC control register return value
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** inputs
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* ''TxRx_Dout'': [out] EC control register write value
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*** ''Clk'': clock
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* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]
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*** ''/Rst'': asynchronous, active-low reset
 
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*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
 
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*** ''TxRx_Done'': ''Done'' signal on transceiver
 
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** outputs
 
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*** ''TxRx_Go'': ''Go'' signal on transceiver
 
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*** ''TxRx_R/W'': ''R/W'' signal on transceiver
 
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*** ''TxRx_A'': ''A_in'' bus on transceiver
 
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*** ''Done'': pulse to signal completion
 
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*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high
 

Latest revision as of 06:22, 5 November 2009

(110) DAC Programmer

The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values.

The mask selects which channels must be altered. Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location. The MSB of the first byte will be channel 0 and the LSB of the fourth byte will be channel 31. Thus, if only channels 5 through 17 are to be programmed, the mask would contain:

First data byte 0 0 0 0 0 1 1 1
Second data byte 1 1 1 1 1 1 1 1
Third data byte 1 1 0 0 0 0 0 0
Fourth data byte 0 0 0 0 0 0 0 0

Programming Details

P-packet Format


The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. The first stage involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows immediately after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the DAC Controller for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered the mask must contain 0's for the corresponding bits. If a requested value exceeds the voltage level hardwired into the FPGA firmware, this maximum value is set instead of that requested by in the P-packet. The responding D-packet will reflect this correction.

The DAC Register is pulsed simultaneously with the DAC controller to record the programmed value. These will later be sent back to the PC for confirmation. (No feedback from the DAC chip itself is possible. Channel 31 is reserved for calibration and is connected to ADC channel 7.) Because the combined duration of these operations exceeds the reception time of the minimum-length packet, the module inhibits the Receiver Interface of the Ethernet Controller for the duration of the programming to prevent incoming packet pileup and receive buffer overload.


Ports

  • Clk: [in] clock
  • Rst: [in] asynchronous reset


Write signals to the DAC Controller and DAC Register

  • DAC_iGo: [out] active-low "Go" signal
  • DACReg_En: Enable (write) signal to DAC Register
  • DAC_Addr: [out] 5-bit DAC channel address
  • DAC_D: [out] 14-bit voltage value for the register and DAC Controller
  • DAC_Done: [in] "Done programming" signal from DAC controller


State Register Control Lines

  • state_En: [out] state register enable (write) signal
  • state_D: [out] (3-bit) state register input
  • state_Q: [in] (3-bit) state register output


Transceiver Control Lines

  • TxRx_Go: [out] "Go" signal to read/write an EC control register byte
  • TxRx_RiW: [out] active-high read, active-low write flag
  • TxRx_Aout: [out] EC control register address (8-bit)
  • TxRx_Din: [in] EC control register return value
  • TxRx_Dout: [out] EC control register write value
  • TxRx_Done: [in] "Done" signal from Transceiver
Retrieved from "https://zeus.phys.uconn.edu/wiki/index.php?title=FPGA_Programmer&oldid=4641"