Latest revision as of 21:13, 6 January 2014

Current Guide to Flashing the Final Production FPGAs

Physical Setup

Use the red Xilinx USB cable box to connect the digital control board to the computer
When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Flashing the Program

Open the Project Navigator
1. On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
If the project doesn't load automatically, load the project file Device.xise
1. Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
2. FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
Edit any source files using Vim outside of the Xilinx software
Right click in the bottom left window on Configure Test Device and select "Rerun All"
1. This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
Run Generate Target PROM/ACE File
Run Manage Configuration Project (iMPACT)
1. This will open up the iMPACT program
2. Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
3. In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
4. TDI should connect to xcf01s_vo20 with the file device.mcs underneath
5. The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
In iMPACT in the top left window click on Create PROM File
1. This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
2. In the window titled "iMPACT Processes" run Generate File
3. When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
Click on Program in the iMPACT Processes window
1. This should erase any previous programming and flash the new program onto the FPGA

Igor's Guide to Flashing the First Prototype FPGA

Physical Setup

Use the red Xilinx USB cable box to connect the digital control board to the computer.
The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Editing the uParam program

Open Xilinx ISE Project Manager
In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
Select uParam within FPGA_ctrl.
To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
- This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
The maximum gainmode value can be changed similarly.
Save the file.
There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.

Flashing the program

Now that the program has been changed and saved, open the Xilinx IMPACT program.
Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
Open fpga.ipf
There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
- EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
- FPGA on right, volatile and forgets its programming at every powerdown
Make sure that the digital board has power.
Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
The following settings should be used when creating the PROM
- Xilinx flash/prom
- PROM family platform flash
- Device xcf01s [1M]. Add if not already there.
- Output file name: fpga
- Save to /TotalTest
- Format mcs
- Don't add non-config data.
- Generate
Switch back to the boundary scan tab.
Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.

@@ Line 1: / Line 1: @@
-The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it.  This article discusses the programming of the FPGA.  All code is written in [http://en.wikipedia.org/wiki/VHDL VHDL].  For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
+= Current Guide to Flashing the Final Production FPGAs =
+==Physical Setup ==
+*Use the [http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm red Xilinx USB cable box] to connect the digital control board to the computer
+*When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
+*When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming
-''Open question:'' What is the clock speed of the FPGA?  Timing constraints must be taken into account to link the multiple blocks.
+== Xilinx Software ==
+We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
-== The DAC ==
+=== Flashing the Program ===
+#Open the Project Navigator
+##On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
+#If the project doesn't load automatically, load the project file Device.xise
+##Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
+##FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
+#Edit any source files using Vim outside of the Xilinx software
+#Right click in the bottom left window on Configure Test Device and select "Rerun All"
+##This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
+#Run Generate Target PROM/ACE File
+#Run Manage Configuration Project (iMPACT)
+##This will open up the iMPACT program
+##Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
+##In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
+##TDI should connect to xcf01s_vo20 with the file device.mcs underneath
+##The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
+#In iMPACT in the top left window click on Create PROM File
+##This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
+##In the window titled "iMPACT Processes" run Generate File
+##When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
+#Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
+#Click on Program in the iMPACT Processes window
+##This should erase any previous programming and flash the new program onto the FPGA
-=== Interface ===
+= Igor's Guide to Flashing the First Prototype FPGA =
+== Physical Setup ==
+*Use the red Xilinx USB cable box to connect the digital control board to the computer.
+*The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
+*2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
-The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal.  A serial communication transfers one 19-bit word:
+== Xilinx Software ==
-{| align="center" cellpadding="1" border="1" cellspacing="1"
+We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
-|
-{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
-! colspan="5" text-align:left" | A
-! colspan="14" text-align:left" | DB
-|-
-| 04 || 03 || 02 || 01 || 00 || 13 || 12 || 11 || 10 || 09 || 08 || 07 || 06 || 05 || 04 || 03 || 02 || 01 || 00
-|}
-|}
-* A(4:0) is a 5-bit address to select the target DAC channel.  A4 is the most-significant bit and transfers first.
+=== Editing the uParam program ===
-* DB(13:0) is a 14-bit voltage code, where <math>V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}</math>.
+*Open Xilinx ISE Project Manager
-** DB = 0 yields <math>V_{out} = 0</math>.
+*In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
-** DB = <math>2^{14}-1</math> (full scale) yields <math>V_{out} = 49.9969*V_{RefIn}</math>.
+*Select uParam within FPGA_ctrl.
+*To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
+**This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
+*The maximum gainmode value can be changed similarly.
+*Save the file.
+*There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
-The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''.  A write to the DAC begins with a falling edge of ''SYNC''.  The next 19 bits (counted off by ''SCLK'') are saved into a shift register  The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt.  A minimum of 200ns is required between exchanges.  ''SCLK'' is ignored except during the 19 shift cycles.  The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically.  In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz.  For further details on timing and protocol, see the AD5535 data sheet supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
+=== Flashing the program ===
+*Now that the program has been changed and saved, open the Xilinx IMPACT program.
-=== Emulator ===
+*Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
+*Open fpga.ipf
-[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]
+*There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
+**EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
-The functional block diagram for the emulator is shown to the right.  The blocks are:
+**FPGA on right, volatile and forgets its programming at every powerdown
-* '''19-cycle hold'''
+*Make sure that the digital board has power.
-** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data.  It ignores any additional pulses while the 19-cycle pulse is running.  It also enforces a gap of one cycle between serial words.
+*Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
-** inputs
+*The following settings should be used when creating the PROM
-*** ''Reset'': asynchronous, active-low reset
+**Xilinx flash/prom
-*** ''CLK'': clock
+**PROM family platform flash
-*** ''Begin'': active-low input pulse
+**Device xcf01s [1M]. Add if not already there.
-** outputs
+**Output file name: fpga
-*** ''Go'': 19-cycle pulse
+**Save to /TotalTest
-* '''shift register'''
+**Format mcs
-** This is a serial-in, parallel-out, 19-bit shift register.  While the enable line is high it clocks in data.  The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
+**Don't add non-config data.
-** inputs
+**Generate
-*** ''Reset'': asynchronous, active-low reset
+*Switch back to the boundary scan tab.
-*** ''D_in'': data-in serial line
+*Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.
-*** ''En'': enable
-*** ''Clk'': clock
-** outputs
-*** ''Addr'': 5-bit parallel address bus
-*** ''Code'': 14-bit parallel code bus
-* '''follow pulse'''
-** This block monitors the enable line generated by the 19-cycle hold block.  At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.
-** inputs
-*** ''Reset'': asynchronous, active-low reset
-*** ''Clk'': clock
-*** ''D'': 19-cycle input pulse
-** outputs
-*** ''Q'': single-cycle following pulse
-* '''5-to-32 demux'''
-** This block is a 5-to-32 demultiplexer.  It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.
-** inputs
-*** ''Select'': 5-bit-wide select bus
-*** ''Data'': data line
-** outputs
-*** ''00:31'': 32 enable lines (on per terminal register)
-* '''terminal register''' (x32)
-** This is a 14-bit, parallel-in, parallel-out register.  There is one terminal register for every channel.
-** inputs
-*** ''Reset'': asynchronous, active-low reset
-*** ''Clk'': clock
-*** ''D'': 14-bit data bus
-*** ''En'': read enable
-** outputs
-*** ''Q'': 14-bit output bus
-=== Controller ===
-[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]
-The functional block diagram for the controller is shown to the right.  The blocks are:
-* '''19-cycle hold'''
-** Identical to the component of the same name in the DAC emulator (see above)
-* '''delay'''
-** Delays all signals by one clock cycle
-** inputs
-*** ''Clk'': clock
-*** ''D'': signal in
-** outputs
-*** ''Q'': signal out
-* '''shift register'''
-** A 19-bit, parallel-in, serial-out shift register.  It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high.  The signal is MSB of Addr to LSB of Code.
-** inputs
-*** ''Clk'': clock
-*** ''Reset'': asynchronous, active-low reset
-*** ''Addr'': 5-bit address bus
-*** ''Code'': 14-bit code bus
-*** ''Sh/Ld'': positive-logic shift/negative-logic load
-** outputs
-*** ''Q'': serial out line
-== The Temperature Sensor ==
-=== Interface ===
-The AD7314 temperature sensor uses a four-wire interface related to (and compatible with) the [http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus SPI bus] protocol.  The wires are:
-* ''CE'': Chip Enable (input), positive logic enable for ''SCLK''
-* ''SCLK'': Serial Clock (input), clock line supplied by external source
-* ''SDI'': Serial Data In (input), data input line
-* ''SDO'': Serial Data Out (output), data output line
-Note that the input/output notations are for slave devices (such as the temperature sensor) but are reversed for master devices (such as the FPGA).  Proper SPI protocol flips the I/O polarity of ''CE'' and ''SCLK'' and crosses the ''SDI'' and ''SDO'' lines so that ''SDI'' is an input on every device and ''SDO'' is always an output.  To maintain simplicity in wiring conventions we are not using proper SPI protocol, but are calling the slave input/master output line ''SDI'' and the slave output/master input line ''SDO'' so that the ''SDI/O'' notations are proper for slaves.  The maximum clock rate is no higher than 10MHz.  The interface, having separate input and output lines, is full-duplex; in fact the temperature sensor is unable to function in half-duplex mode.  Outputs from the temperature sensor change on rising edges of ''SCLK'', but inputs are latched on falling edges.
-There is only one write operation to the temperature sensor and that is used to direct the temperature sensor to enter power-down mode.  We do not plan to use this mode, so the ''SDI'' input on the temperature sensor will be tied to ground.
-A read operation occurs during a 16-cycle pulse of ''CE''.  The first transmitted bit will be zero, followed by ten bits of temperature data (MSB first).  The remaining five bits are copies of the final data bit.  After ''CE'' goes low ''SDO'' goes into a high-Z state.  Temperature data is given in degrees Celsius.  The format is two's-complement with two decimal places; in essence it is standard two's-complement, then the result must be divide by four after converting to decimal.
-=== Emulator ===
-[[Image:Temp Emulator Block.JPG|thumb|Temperature sensor emulator functional block diagram]]
-The functional block diagram for the emulator is shown to the right.  The blocks are:
-* '''Error Flag'''
-** The error flag goes high if the enable line is high for 1-15 or 17+ cycles.  It resets to low any time the enable line goes back to high.  It is used to notify of a "bad" transmission (not 16 cycles long).
-** inputs
-*** ''Clk'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''En'': enable
-** outputs
-*** ''Err'': error flag
-* '''
-=== Controller ===
-[[Image:Temp Controller Block.JPG|thumb|Temperature sensor controller functional block diagram]]

Difference between revisions of "Programming the FPGA"

Latest revision as of 21:13, 6 January 2014

Contents

Current Guide to Flashing the Final Production FPGAs

Physical Setup

Xilinx Software

Flashing the Program

Igor's Guide to Flashing the First Prototype FPGA

Physical Setup

Xilinx Software

Editing the uParam program

Flashing the program

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