Difference between revisions of "FPGA Querier"

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:''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''
 
:''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''
  
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== (100) Query Sensor Chips ==
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= (100) Query Sensor Chips =
  
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The Querier performs a poll of the sensor chips: Temperature Sensor and the 8-channel ADC. The returned values from these combined nine polls are stored in the [[FPGA_Registers#Temperature Register|Temperature and ADC registers]].
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The Querier performs a poll of the sensor chips: Temperature Sensor and the 8-channel ADC. The returned values from these combined nine polls are stored in the [[FPGA_Registers#Temperature Register|Temperature and ADC registers]]. The Querier always passes control to the Transmitter in order to relay an S (status) packet to the PC with the polled values.
  
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Minor error-handling is built into this module. When the 3-bit ADC address returned from the [[Programming_the_SPI|SPI module]] after a query does not match the requested channel, a 0xFFF value is written for that voltage value.
  
  
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== Programming Details ==
  
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The Querier polls the [http://zeus.phys.uconn.edu/wiki/index.php/SiPM_digital_control_board#Temperature_sensor Temperature Sensor] and the 8 channels of the [http://zeus.phys.uconn.edu/wiki/index.php/SiPM_digital_control_board#The_ADC ADC], by shuffling down in channel number and polling child modules that handle the chip interfacing.
  
  
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This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC.  Its job is to update all status values from the status chips in preparation for transmission.  Additionally, it converts all values to 16-bit two's-complement before storing locally.  Once all status values have been updated it transitions to state 101.
 
  
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Currently we assume that data values will be stored in the FPGA.  If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.
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=== Ports ===
  
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inputs
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* ''Clk'': [in] clock
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* ''Clk'': clock
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* ''Rst: [in] asynchronous reset
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* ''/Rst'': asynchronous, active-low reset
 
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* ''State'': 3-bit state value
 
  
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internal signals
 
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* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
 
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* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
 
  
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blocks
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SPI bus lines
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* '''ADC Poll'''
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* ''SPI_SCLK'': [out] 5MHz clock feed-through
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** Updates values stored in the FPGA from the ADC.  Obtains data from ADC, converts to 16-bit two's-complement, and stores.
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* ''SPI_T_CE'': [out] Temp. sensor chip enable
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** inputs
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* ''SPI_A_iCS'': [out] ADC active-low chips select
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*** ''Clk'': clock
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* ''SPI_SDI'': [out] SPI (Temp sensor/ADC) input line
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*** ''/Rst'': asynchronous, active-low reset
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* ''SPI_SDO'': [in] SPI output - return values for the FPGA
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*** ''Go'': go pulse to begin
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** outputs
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*** - All ADC control lines -
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Temperature and ADC value storage
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*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
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* ''ADCreg_En'': [out] write signal to ADC register
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*** ''En'': enable line for writing to the internal registers
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* ''ADCreg_A '': [out] 3-bit address selection for ADC register
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*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
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* ''ADCred_D'': [out] 12-bit ADC value output to the ADC register
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*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
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* ''Tempreg_En'': [out] write signal to Temperature register
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* '''Temp Poll'''
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* ''Tempreg_D'': [out] 10-bit Temperature value output to the Temperature register
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** Updates value stored in the FPGA from the temperature sensor.  Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
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** inputs
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*** ''Clk'': clock
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[[FPGA_Registers#State_Register|State Register]] Control Lines
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*** ''/Rst'': asynchronous, active-low reset
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* ''state_En'': [out] state register enable (write) signal
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*** ''Go'': go pulse to begin
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* ''state_D'': [out] (3-bit) state register input
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** outputs
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* ''state_Q'': [in] (3-bit) state register output
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*** - All temperature sensor control lines -
 
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*** ''En'': enable line for writing to the internal register
 
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*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
 
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* '''Coordinator'''
 
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** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
 
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** inputs
 
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*** ''Clk'': clock
 
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*** ''/Rst'': asynchronous, active-low reset
 
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*** ''A_Done'': high when ADC is done polling
 
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** outputs
 
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*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
 
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**: Note that the temperature sensor does not signal completion.  That is because the temperature sensor need only update one value, while the ADC must update eight values.  Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
 
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*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high
 

Latest revision as of 19:23, 12 October 2010

See also Programming the Ethernet Controller for a survey of modules and a general discussion of FPGA design approach.

(100) Query Sensor Chips

The Querier performs a poll of the sensor chips: Temperature Sensor and the 8-channel ADC. The returned values from these combined nine polls are stored in the Temperature and ADC registers. The Querier always passes control to the Transmitter in order to relay an S (status) packet to the PC with the polled values.

Minor error-handling is built into this module. When the 3-bit ADC address returned from the SPI module after a query does not match the requested channel, a 0xFFF value is written for that voltage value.


Programming Details

The Querier polls the Temperature Sensor and the 8 channels of the ADC, by shuffling down in channel number and polling child modules that handle the chip interfacing.


Ports

  • Clk: [in] clock
  • Rst: [in] asynchronous reset


SPI bus lines

  • SPI_SCLK: [out] 5MHz clock feed-through
  • SPI_T_CE: [out] Temp. sensor chip enable
  • SPI_A_iCS: [out] ADC active-low chips select
  • SPI_SDI: [out] SPI (Temp sensor/ADC) input line
  • SPI_SDO: [in] SPI output - return values for the FPGA


Temperature and ADC value storage

  • ADCreg_En: [out] write signal to ADC register
  • ADCreg_A : [out] 3-bit address selection for ADC register
  • ADCred_D: [out] 12-bit ADC value output to the ADC register
  • Tempreg_En: [out] write signal to Temperature register
  • Tempreg_D: [out] 10-bit Temperature value output to the Temperature register


State Register Control Lines

  • state_En: [out] state register enable (write) signal
  • state_D: [out] (3-bit) state register input
  • state_Q: [in] (3-bit) state register output
Retrieved from "https://zeus.phys.uconn.edu/wiki/index.php?title=FPGA_Querier&oldid=5186"