SiPM Amplifier Optimization

The SiPM amplifier currently in use for SiPM characterization (Photonique item "AMP_0604") must be adapted for tagger microscope use. The following is a brief outline of the design requirements. They are discussed in detail in the following sections

1. adjustable gain, ranging from readout of hundreds of pixels to calibration with single-photon counting
2. less than 15% gain variability on transistor $\beta$ ($h_{FE}$) parameter
3. summing circuit to pool SiPM signals in groups of 5 (readout of individual channels must not affect readout of the some regardless of termination used)
4. minimized pulse duration for higher running rates
5. minimized power consumption

Design Requirements

One of the most important considerations in the amplifier design is the target data acquisition system. Currently, the microscope is slated to be read out by a 12-bit flash ADC with a 250 MHz sampling rate and range settings of -2V, -1V and -0.5V.

Gain

The amplifier provided by Photonique with a gain of roughly 3 kΩ was well suited for single photon counting. However, for typical signals ranging in the hundreds of SiPM pixels, this gain excessive. However, the option of switching back to single photon detection for the purposes of calibration would be a nice feature.

From the perspective of expected signal amplitudes (taking into account optical and SiPM's quantum efficiencies) signals around 300 pixels (px) are expected. With a SiPM gain of about 2e5 ~ 9.6 pC are expected to be deposited. Design uncertainties that go into the full calculation summarized here can easily allow variation in this result by a factor of two or more. Roughly estimating this charge to be contained in a triangular pulse with 5 ns FWHM (after all the broadening inherent in the amplifier) yields a total signal peak of 0.5 mA. With this figure and the full range of the ADC (2V) it seems that 3 kΩ is still appropriate. However this does not leave room for variation discussed above. Instead, a goal of sub-1 kΩ gain was adopted.

For the high gain setting, the issue is mainly the vertical resolution of the ADC. For most of the duration of this project, the 8-bit version of the ADC was planned to be allocated for microscope readout, imposing a stringent requirement on gain in order to avoid the digitization noise inherent in signals only a few adc voltage steps. The 12-bit ADC makes clean readout of single pixel wavefunctions more realistic: at the most sensitive scale of 0.5 V, the resolution is 0.12 mV. However, we must also take into account noise and a possible factor of two loss in the split of the signal between the ADC and the CFD (constant fraction discriminator to prepare for time pick-off.) This time, it is appropriate to take a pessimistic scenario of the pulse shape: taking a triangular pulse with 30 ns FWHM, leading to a single pixel current peak of 0.27*nbsp;μA. Under these conditions, gain of 7 kΩ is enough, giving 15 adc steps per pixel.

Going from this integrates charge figure to actual signal heights requires knowledge of the pulse duration due to pulse shaping in the amplifier. However, gain and pulse shape are coupled in the amplifier design - one resetting the goals for the other.

The initial approach to this problem of gain switching was just that suggested by Photonique documentation: turning up the amplifier supply voltage. With the transistors' maximal voltage rating of 15 V taken as high gain setting, some simulations done to assess the amplifier performance.

The amplifier provided by Photonique with a gain of roughly 3 kΩ was well suited for single photon counting. However, for typical signals ranging in the hundreds of SiPM pixels, this gain excessive. However, the option of switching back to single photon detection for the purposes of calibration would be a nice feature. The initial approach to this problem of gain switching was just that suggested by Photonique documentation: turning up the amplifier supply voltage. With the transistors' maximal voltage rating of 15 V taken as high gain setting, some simulations done to assess the amplifier performance. The following problems were found in this approach:

• Gain saturates with increasing supply voltage leading to poor gain separation between the two modes (recall that the low gain setting needs to be much lower for real signals.)
• Power consumption is of order 200 mW at high gain setting
• Component values necessary for high gain are not suitable for stable, $\beta$-independent design
• Input impedance of the amplifier increase significantly in the high gain design. On the other hand, the effective impedance and therefore pulse shape varies with supply voltage.

A low-impedance input stage was designed to alleviate the last issue, but the rest remained serious concerns and challenges. An alternate design was adapted in which the summing stage further amplifies the signal. Now, however, instead of doing this with supply