Reset and Initialization - Revision history

Senderovich at 17:12, 6 November 2009

2009-11-06T17:12:42Z

Senderovich at 21:40, 5 June 2008

2008-06-05T21:40:53Z

Senderovich: /* The Ethernet controller */

2008-04-14T20:49:21Z

The Ethernet controller

Senderovich: /* The Ethernet controller */

2007-09-10T21:55:41Z

The Ethernet controller

Krueger at 19:01, 17 July 2007

2007-07-17T19:01:33Z

Krueger at 19:00, 17 July 2007

2007-07-17T19:00:59Z

Krueger at 18:49, 17 July 2007

2007-07-17T18:49:11Z

New page

On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle|reset the system on a command from the PC]].

== The DAC ==

The AD5535 DAC has an active-low reset pin. Pulling that pin low will reset the DAC, zeroing all channels.

== The temperature sensor ==

The AD7314 temperature sensor does not have a reset function. It self-initializes on powering up.

== The ADC ==

The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up. The reset procedure is to hold the ''D<sub>in</sub>'' line high while performing two dummy conversions. During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA. It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.

== The Ethernet controller ==

The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization"). The main points of the process will be covered here.
* The first step is to wait for the reset pin to rise. No flag will be raised upon the completion of this step other than the reset pin (which is an input to the CP2200/1) being high.
* The second step is to wait for Oscillator Initialization to complete. Completion of this will be signaled by an interrupt request signal.
* The third step is to wait for Self Initialization to complete. Completion of this will also be signaled by an interrupt request signal.
* At this point all interrupts will be enabled. Any interrupts which the FPGA will not handle should be disabled now.
* The physical layer must be initialized, which is itself a multi-step process.
** See section 15.7 "Initializing the Physical Layer"
** If auto-negotiation is to be used see section 15.2 "Auto-Negotiation Synchronization."
* Enable the Link, Act, or Activity/Link LED(s).
* The MAC must now be initialized, another multi-step subprocess.
** See section 14.1 "Initializing the MAC."
* The receive filter must now be configured.
** See section 12.4 "Initializing the Receive Buffer, Filter and Hash Table."
* The CP2200/1 is now ready for regular operation.

This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing the board and the PC are unable to communicate.

@@ Line 1: / Line 1: @@
-On start-up the FPGA must reset and initialize each component; especially the Ethernet controller.  Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle|reset the system on a command from the PC]].
+On start-up the FPGA must reset and initialize each component; especially the Ethernet controller (EC).  Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle|reset the system on a command from the PC]].
-== The DAC ==
+== Reset Requirements by Component ==
 The AD5535 DAC has an active-low reset pin.  Pulling that pin low will reset the DAC, zeroing all channels.
-== The temperature sensor ==
+=== The temperature sensor ===
 The AD7314 temperature sensor does not have a reset function.  It self-initializes on powering up.
-== The ADC ==
+=== The ADC ===
 The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up.  The reset procedure is to hold the D<sub>in</sub> line high while performing two dummy conversions.  During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA.  It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.
-== The Ethernet controller ==
+=== The Ethernet controller ===
 The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization").  The main points of the process will be covered here.
@@ Line 33: / Line 35: @@
 See [http://www.google.com/notebook/public/08003089451145463058/BDQm4IgoQs_jkx-4i Ethernet Controller Reset Sequence notes] for more information and specifics of implementation.

← Older revision		Revision as of 21:40, 5 June 2008
Line 1:		Line 1:
−	~~'''This page discusses a component that is currently in development. The information on this page may evolve as the project progresses.'''~~
−
	On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle\|reset the system on a command from the PC]].		On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle\|reset the system on a command from the PC]].

← Older revision		Revision as of 20:49, 14 April 2008
Line 33:		Line 33:

	This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing, the board and the PC are unable to communicate.		This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing, the board and the PC are unable to communicate.
		+
		+	See [http://www.google.com/notebook/public/08003089451145463058/BDQm4IgoQs_jkx-4i Ethernet Controller Reset Sequence notes] for more information and specifics of implementation.

← Older revision		Revision as of 21:55, 10 September 2007
Line 32:		Line 32:
	* The CP2200/1 is now ready for regular operation.		* The CP2200/1 is now ready for regular operation.

−	This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing the board and the PC are unable to communicate.	+	This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing, the board and the PC are unable to communicate.

← Older revision		Revision as of 19:00, 17 July 2007
Line 1:		Line 1:
		+	'''This page discusses a component that is currently in development. The information on this page may evolve as the project progresses.'''
		+
	On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle\|reset the system on a command from the PC]].		On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle\|reset the system on a command from the PC]].