Programming the FPGA - Revision history

Barnes at 21:13, 6 January 2014

2014-01-06T21:13:06Z

Barnes at 14:49, 18 October 2013

2013-10-18T14:49:11Z

Barnes at 19:07, 9 April 2012

2012-04-09T19:07:13Z

Barnes at 19:00, 9 April 2012

2012-04-09T19:00:51Z

Barnes at 19:53, 5 April 2012

2012-04-05T19:53:37Z

Senderovich at 21:32, 5 June 2008

2008-06-05T21:32:27Z

Krueger at 19:53, 20 July 2007

2007-07-20T19:53:57Z

Krueger at 18:59, 17 July 2007

2007-07-17T18:59:55Z

Krueger at 18:49, 17 July 2007

2007-07-17T18:49:30Z

Krueger at 18:48, 17 July 2007

2007-07-17T18:48:56Z

@@ Line 1: / Line 1: @@
-= Physical Setup =
+= Current Guide to Flashing the Final Production FPGAs =
 *Use the red Xilinx USB cable box to connect the digital control board to the computer.
 *The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
 *2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
-= Xilinx Software =
+== Xilinx Software ==
 We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
-== Editing the uParam program ==
+=== Editing the uParam program ===
 *Open Xilinx ISE Project Manager
 *In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
@@ Line 18: / Line 52: @@
 *There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
-== Flashing the program ==
+=== Flashing the program ===
 *Now that the program has been changed and saved, open the Xilinx IMPACT program.
 *Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date

← Older revision		Revision as of 14:49, 18 October 2013
Line 5:		Line 5:

	= Xilinx Software =		= Xilinx Software =
		+
		+	We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

	== Editing the uParam program ==		== Editing the uParam program ==

← Older revision		Revision as of 19:07, 9 April 2012
Line 23:		Line 23:
	**EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)		**EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
	**FPGA on right, volatile and forgets its programming at every powerdown		**FPGA on right, volatile and forgets its programming at every powerdown
		+	*Make sure that the digital board has power.
		+	*Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
		+	*The following settings should be used when creating the PROM
		+	**Xilinx flash/prom
		+	**PROM family platform flash
		+	**Device xcf01s [1M]. Add if not already there.
		+	**Output file name: fpga
		+	**Save to /TotalTest
		+	**Format mcs
		+	**Don't add non-config data.
		+	**Generate
		+	*Switch back to the boundary scan tab.
		+	*Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.

← Older revision		Revision as of 19:00, 9 April 2012
Line 1:		Line 1:
−	~~Soon~~ to be ~~added~~: ~~Directions~~ on ~~how to flash~~ the FPGA	+	= Physical Setup =
		+	*Use the red Xilinx USB cable box to connect the digital control board to the computer.
		+	*The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
		+	*2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
		+
		+	= Xilinx Software =
		+
		+	== Editing the uParam program ==
		+	*Open Xilinx ISE Project Manager
		+	*In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
		+	*Select uParam within FPGA_ctrl.
		+	*To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
		+	**This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
		+	*The maximum gainmode value can be changed similarly.
		+	*Save the file.
		+	*There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
		+
		+	== Flashing the program ==
		+	*Now that the program has been changed and saved, open the Xilinx IMPACT program.
		+	*Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
		+	*Open fpga.ipf
		+	*There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
		+	**EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
		+	**FPGA on right, volatile and forgets its programming at every powerdown

← Older revision	Revision as of 19:53, 5 April 2012
Line 1:	Line 1:
−	+	Soon to be added: Directions on how to flash the FPGA

← Older revision		Revision as of 21:32, 5 June 2008
Line 1:		Line 1:
−	~~[[Image:Spartan.jpg\|right]]~~

−	The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in [[VHDL_tutorial\|VHDL]]. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
−
−	~~== Open questions ==~~
−
−	~~Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.~~
−	* What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
−	* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component. This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip. ''Work in progress'': see [[Reset and Initialization]].
−	* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
−	* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
−	* A core VHDL module is needed to tie all the components together. The Ethernet controller module may take on the role of FPGA core.
−
−	~~== Component code ==~~
−
−	* [[Programming the DAC]]
−	* [[Programming the SPI]]
−	* [[Programming the Ethernet controller]]
−	* [[Reset and Initialization]]

@@ Line 15: / Line 15: @@
 * [[Programming the DAC]]
-* [[Programming the temperature sensor]]
+* [[Programming the SPI]]
 * [[Programming the Ethernet controller]]
 * [[Reset and Initialization]]

@@ Line 7: / Line 7: @@
 Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
 * What is the clock speed of the FPGA?  Timing constraints must be taken into account to link the multiple blocks.
-* Current designs (11 July, 2007) account for normal activity.  Need to design modules/logic for startup and initialization of each component.  This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.
+* Current designs (11 July, 2007) account for normal activity.  Need to design modules/logic for startup and initialization of each component.  This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.  ''Work in progress'': see [[Reset and Initialization]].
 * Do the parts work on falling or rising edges of the clock?  Most VHDL designs are currently on rising edges, but this can be easily corrected.
 * The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
 == Component code ==

← Older revision		Revision as of 18:49, 17 July 2007
Line 18:		Line 18:
	* [[Programming the Ethernet controller]]		* [[Programming the Ethernet controller]]
	* [[Reset and Initialization]]		* [[Reset and Initialization]]
−
−	~~== Reset and Initialization ==~~
−
−	On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle\|reset the system on a command from the PC]].
−
−	~~=== The DAC ===~~
−
−	~~The AD5535 DAC has an active-low reset pin. Pulling that pin low will reset the DAC, zeroing all channels.~~
−
−	~~=== The temperature sensor ===~~
−
−	~~The AD7314 temperature sensor does not have a reset function. It self-initializes on powering up.~~
−
−	~~=== The ADC ===~~
−
−	The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up. The reset procedure is to hold the ''D<sub>in</sub>'' line high while performing two dummy conversions. During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA. It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.
−
−	~~=== The Ethernet controller ===~~
−
−	~~The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization"). The main points of the process will be covered here.~~
−	* The first step is to wait for the reset pin to rise. No flag will be raised upon the completion of this step other than the reset pin (which is an input to the CP2200/1) being high.
−	* The second step is to wait for Oscillator Initialization to complete. Completion of this will be signaled by an interrupt request signal.
−	* The third step is to wait for Self Initialization to complete. Completion of this will also be signaled by an interrupt request signal.
−	* At this point all interrupts will be enabled. Any interrupts which the FPGA will not handle should be disabled now.
−	* The physical layer must be initialized, which is itself a multi-step process.
−	** See section 15.7 "Initializing the Physical Layer"
−	** If auto-negotiation is to be used see section 15.2 "Auto-Negotiation Synchronization."
−	* Enable the Link, Act, or Activity/Link LED(s).
−	* The MAC must now be initialized, another multi-step subprocess.
−	** See section 14.1 "Initializing the MAC."
−	* The receive filter must now be configured.
−	** See section 12.4 "Initializing the Receive Buffer, Filter and Hash Table."
−	* The CP2200/1 is now ready for regular operation.
−
−	This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing the board and the PC are unable to communicate.

@@ Line 17: / Line 17: @@
 * [[Programming the ADC]]
 * [[Programming the Ethernet controller]]
 == Reset and Initialization ==