Programming the Ethernet controller - Revision history

Senderovich: /* State-Module organization */

2009-11-05T06:33:45Z

State-Module organization

2009-10-29T03:25:33Z

2009-10-29T03:20:14Z

State-Module organization

2008-06-05T23:21:41Z

Combined control flow

2008-06-05T22:25:50Z

2008-06-05T22:24:26Z

Combined control flow

2008-06-05T22:24:05Z

Combined control flow

2008-06-02T18:23:55Z

2008-05-29T17:29:36Z

2008-05-19T20:01:13Z

@@ Line 30: / Line 30: @@
 | align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 100
 |-
-| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
+| align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 100
 |-
 | align="center" | 010 || [[FPGA_Idler|Idler]] || align="left" | This is the active module during the FPGA's default idle state. It awaits the "Receive FIFO buffer not empty" interrupt and passes control to the Reader || 011
@@ Line 43: / Line 43: @@
 |-
 |}
 === State interconnect ===

@@ Line 43: / Line 43: @@
 |-
 |}
 === State interconnect ===
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 This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20&nbsp;MHz; clock to generate the "slow" 5&nbsp;MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information.
 == Combined control flow ==
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 [[Image:DigBoardScheme.png|center]]
 = Emulator =
@@ Line 95: / Line 98: @@
 * Non-state Modules
 ** [[FPGA_Transceiver|Transceiver]]
 ** [[FPGA_Registers|Registers]]
 * [[Ethernet_packets|Ethernet Packet formatting]]

@@ Line 28: / Line 28: @@
 ! State !! Module Name !! Description !! Succeeding State
 |-
-| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 101
+| align="center" | 000 || [[FPGA_Reset|Reset]]_hard || align="left" |Coordinates the reset and start-up of the EC. || 100
 |-
 | align="center" | 001 || [[FPGA_Reset|Reset]]_soft || align="left" | Extends the reset to the PC-requested chips and records PC's MAC for later communication. || 101
@@ Line 43: / Line 43: @@
 |-
 |}
 === State interconnect ===

← Older revision		Revision as of 23:21, 5 June 2008
Line 76:		Line 76:

	[[Image:DigBoardScheme.png\|center]]		[[Image:DigBoardScheme.png\|center]]
−
−
−
−

	= Emulator =		= Emulator =

@@ Line 48: / Line 48: @@
 As described above, these states form the outline of the functional block diagram. This implementation calls for a central ''state register''.  Each block reads the state value in the register and enables itself upon seeing its own value.  After completion of its function, a block will write a new value to the state register to enable the next block. With several modules writing to the register, usual precautions must be taken to avoid more than one drivers forcing a line simultaneously. All modules must be designed to go to high impedance on their output lines when they are not active.
 == Interface ==
@@ Line 69: / Line 77: @@
 [[Image:DigBoardScheme.png|center]]

@@ Line 61: / Line 61: @@
 == Combined control flow ==
-[[Image:OperationCourse.png|thumb|340px|Operation course between the digital board and the controller PC]]
+[[Image:OperationCourse.png|frame|Operation course between the digital board and the controller PC]]
 Conceptually, the operation course must proceed as outlined in the adjacent figure. The main concern in the tagger control is maintaining a map between board/channel addresses and actual energy bins. For this purpose, the diagrammed two-stage reset plan was devised in the course of which the FPGA learns the PC's MAC address and the PC builds a MAC-Location lookup table. (The "Location" is an 8-byte slot identifier which allows the PC to pinpoint the SiPM channel group.)

@@ Line 1: / Line 1: @@
-The modules involved in communication with the Ethernet Controller chip (EC) serve as the core of the FPGA. The different tasks that need to be performed by these modules include
+The modules involved in communication with the Ethernet Controller chip (EC) serve as the core of the FPGA. The tasks that need to be performed by these modules include
 * executing the complex board reset and address lookup sequence
 * polling for new packets and switching execution accordingly

← Older revision		Revision as of 20:01, 19 May 2008
Line 93:		Line 93:
	** [[FPGA_Registers]]		** [[FPGA_Registers]]

−	* [[~~Ethernet_Packets~~\|Ethernet Packet formatting]]	+	* [[Ethernet_packets\|Ethernet Packet formatting]]