Senderovich at 23:01, 6 June 2008

2008-06-06T23:01:05Z

Senderovich at 18:52, 16 May 2008

2008-05-16T18:52:57Z

New page

= Transceiver =

This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; hey simply order a start of transfer and wait for notification of the transfer's completion. The transceiver for its part initiates a read or write conversation with the CP2200/1 over the multiplex Intel bus upon request from the internals and returns data, if applicable, along with a "Done" pulse at the end of the conversation.

This unit serves as a bridge between the Ethernet Controller chip and the FPGA in terms of timing as well. The latter is run at the rate of its slowest client: the Temperature sensor which has a top recommended clock rate of 10 MHz. Given that CP2200/1 prefers 20 MHz, it was resolved that the FPGA will run on a 5 MHz clock subdivided from the Ethernet Controller's. The transceiver performs this subdivision and ensures data latching on the external and internal buses, as shown in the adjacent diagram.

[[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]]

== I/O Pins ==

inputs
* ''fCLK'': "fast" (20MHz) clock
* ''/Rst'': asynchronous, active-low reset
* ''TxRx_Go'': pulse to begin a transmission
* ''TxRx_RiW'': read/write toggle: active-high read, active-low write
* ''TxRx_Ain'': 8-bit bus for address to read to/write from
* ''TxRx_Din'': 8-bit bus for data to write; ignored during a read

outputs to internals
* ''Done'': pulse to signal completion of a transmission
* <s>''R/W_out'': read/write flag: active-high read, active-low write</s>
* <s>''A_out'': 8-bit bus for address of last read/write</s>
* ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
* ''CLK'' : 5MHz clock for all internals subdivided from the master 20MHz clock.

outputs to CP2200/1
* ''/CS'': active-low chip select
* ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
* ''MuxEn'': Multiplexed flag; not used for CP2201
* ''ALE'': ALE strobe
* ''/Wr'': Active-low write flag
* ''/Rd'': Active-low read flag

inouts
* ''AD'': 8-bit address and data bus

@@ Line 1: / Line 1: @@
 = Transceiver =
-This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; hey simply order a start of transfer and wait for notification of the transfer's completion. The transceiver for its part initiates a read or write conversation with the CP2200/1 over the multiplex Intel bus upon request from the internals and returns data, if applicable, along with a "Done" pulse at the end of the conversation.
+This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; they simply order a start of transfer and wait for notification of the transfer's completion. The transceiver for its part initiates a read or write conversation with the CP2200/1 over the multiplex Intel bus upon request from the internals and returns data, if applicable, along with a "Done" pulse at the end of the conversation.
 This unit serves as a bridge between the Ethernet Controller chip and the FPGA in terms of timing as well. The latter is run at the rate of its slowest client: the Temperature sensor which has a top recommended clock rate of 10 MHz. Given that CP2200/1 prefers 20 MHz, it was resolved that the FPGA will run on a 5 MHz clock subdivided from the Ethernet Controller's. The transceiver performs this subdivision and ensures data latching on the external and internal buses, as shown in the adjacent diagram.
@@ Line 7: / Line 7: @@
 [[Image:MuxIntelTiming.png|frame|Multiplexed Intel Bus and internal I/O timing scheme enforced by FPGA clocks]]
-inputs
+== Programming Details ==
-outputs to internals
+Clock subdivision from 20 MHz to 5 MHz is done in a straightforward with a counter.
-outputs to CP2200/1
+The timing of the Muxed Intel bus conversation with the EC is nicely metered out by the 20 MHz clock. Each half-wave of the fast clock is 25 ns, which turns out to be a convenient multiple with which to count off the required waiting periods. The module has been written carefully to satisfy the timing requirements outlined in the EC manual. As seen in the figure, the entire conversation turns out to take only two slow clock cycles, making the delay for the FPGA internals negligible.
-inouts
+=== Ports ===
 * ''AD'': 8-bit address and data bus

FPGA Transceiver - Revision history

Senderovich at 23:01, 6 June 2008

Senderovich at 18:52, 16 May 2008