FPGA Reusables - Revision history

Senderovich at 23:32, 6 June 2008

2008-06-06T23:32:59Z

Senderovich at 23:31, 6 June 2008

2008-06-06T23:31:42Z

Senderovich at 23:19, 6 June 2008

2008-06-06T23:19:49Z

Senderovich at 23:19, 6 June 2008

2008-06-06T23:19:06Z

Senderovich at 18:55, 16 May 2008

2008-05-16T18:55:52Z

New page

== Reusable Components ==

Several components were found useful as reusable units rather than unique modules. They are listed here roughly from the low level units to high level "wrappers".

=== Read Request (<tt>reqFromAddr</tt>) ===

Sends request for reading (R/W pin high) to the Transceiver at the specified address. (Optionally "Go" pulse can be appropriately delayed in this module to ensure that parameter signals sent to transceiver have gone through their transitions. Currently, these provisions are commented out, relying on clock falling edge latching of the sent data.) This unit is not intended for direct use, but rather to be the core of the fetcher components described here.

=== Write Request (<tt>wrToAddr</tt>) ===

Sends a write request (R/W pin low) to transceiver at the specified address with the specified byte of data. The primary reason of this instruction "packaging" was to obscure the complexity of appropriate delays to ensure proper signal latching. The delayed version is currently commented out under the assumption of falling edge of clock latching of data by the Transceiver.

=== 2-byte Write Request (<tt>wr2BtoAddr</tt>) ===

Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit buffer locations in random memory access. Only the address of the first register needs to be passed in.

=== Byte Fetcher (<tt>getByte</tt>) ===

Fetches a byte of data from the Ethernet Controller registers via the Transceiver. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The actual request is performed via the <tt>reqFromAddr</tt> unit described above, so the timing characteristics are inherited from that module.

=== Auto-reader (<tt>AutoRd</tt>) ===

Performs the same function as the Byte Fetcher (described above) but is hard-wired to address the RXAUTORD (0x01). This is convenient because the Ethernet Controller's AutoRead interface will be used extensively to parse through packets. <tt>AutoRd</tt> is in fact just a wrapper around <tt>GetByte</tt> passing through all signals accept the fixed address input.

=== Random Access Write (<tt>RAwrToAddr</tt>) ===

Writing directly to Ethernet Controller RAM (not to be confused with the control registers) in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time to appropriate control registers and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, as it is out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions.

=== 2-byte Random Access Write (<tt>RAwr2BtoAddr</tt>) ===

Because the data values exchanged between the board and the PC range from 10 to 14 bit depth, zero padded 16-bit words will be used. So, to load this 2-byte word into the transfer buffer requires two random access writes. This module packages this functionality by including two calls to <tt>RAwrToAddr</tt> with address increments and input data latching taken into account.

=== Miscellaneous Components ===

← Older revision		Revision as of 23:32, 6 June 2008
Line 1:		Line 1:
−	The many complex repetitive function of the FPGA call for modules that abstract this complexity or just clean up the code. The following is their list with a brief description of their function. They are listed roughly from the low level units to high level "wrappers".	+	The many complex repetitive function of the FPGA, especially those that concern the Ethernet Controller chip (EC) call for modules that abstract this complexity or just clean up the code. The following is their list with a brief description of their function. They are listed roughly from the low level units to high level "wrappers". The few other modules used repetitively in our code should be self-explanatory.

@@ Line 5: / Line 5: @@
 Fetches a byte of data from the Ethernet Controller registers via the [[FPGA_Transceiver|Transceiver]]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).
@@ Line 17: / Line 22: @@
-Performs the same function as the Byte Fetcher (described above) but is hard-wired to address the RXAUTORD (0x01). This is convenient because the Ethernet Controller's AutoRead interface will be used extensively to parse through packets. <tt>AutoRd</tt> is in fact just a wrapper around <tt>GetByte</tt> passing through all signals accept the fixed address input.
+== 2-byte Random Access Write (<tt>RAwr2BtoAddr</tt>) ==
-Writing directly to Ethernet Controller RAM (not to be confused with the control registers) in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time to appropriate control registers and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, as it is out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions.
+== Interrupt Catcher <tt>INTCatcher</tt> ==
-Because the data values exchanged between the board and the PC range from 10 to 14 bit depth, zero padded 16-bit words will be used. So, to load this 2-byte word into the transfer buffer requires two random access writes.  This module packages this functionality by including two calls to <tt>RAwrToAddr</tt> with address increments and input data latching taken into account.
+This is an essential module for listening to interrupts from the EC. There are relevant interrupts in the reset stage and also when awaiting packets. The four possible interrupts for which the FPGA waits (all others are turned off upon post-reset EC configuration) are selected using a 4-bit mask input bus. The interrupt pin of the EC is monitored directly and read operations of the two interrupt registers commence upon the interrupt line going low. If the requested interrupt has in fact occurred a "Done" is returned.

@@ Line 4: / Line 4: @@
 == Byte Fetcher (<tt>getByte</tt>) ==
-Fetches a byte of data from the Ethernet Controller registers via the [FPGA_Transceiver|Transceiver]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).
+Fetches a byte of data from the Ethernet Controller registers via the [[FPGA_Transceiver|Transceiver]]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).
 == Write Request (<tt>wrToAddr</tt>) ==
-Sends a write request (R/W pin low) to [FPGA_Transceiver|Transceiver] at the specified address with the specified byte of data. The module awaits the "Done" signal from the Transceiver and passes it to the calling module.
+Sends a write request (R/W pin low) to [[FPGA_Transceiver|Transceiver]] at the specified address with the specified byte of data. The module awaits the "Done" signal from the Transceiver and passes it to the calling module.
 == 2-byte Write Request (<tt>wr2BtoAddr</tt>) ==
-Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit locations pointers in random memory access. Only the address of the first register is passed in. Naturally <tt>[[FPGA_Reusables#Write Request (<tt>wrToAddr</tt>)|wrToAddr]]</tt> is used for the individual byte writes.
+Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit locations pointers in random memory access. Only the address of the first register is passed in. Naturally <tt>[[FPGA_Reusables#Write Request (wrToAddr)|wrToAddr]]</tt> is used for the individual byte writes.

@@ Line 1: / Line 1: @@
-== Reusable Components ==
+The many complex repetitive function of the FPGA call for modules that abstract this complexity or just clean up the code. The following is their list with a brief description of their function. They are listed roughly from the low level units to high level "wrappers".
-=== Read Request (<tt>reqFromAddr</tt>) ===
+== Byte Fetcher (<tt>getByte</tt>) ==
-Sends request for reading (R/W pin high) to the Transceiver at the specified address. (Optionally "Go" pulse can be appropriately delayed in this module to ensure that parameter signals sent to transceiver have gone through their transitions. Currently, these provisions are commented out, relying on clock falling edge latching of the sent data.) This unit is not intended for direct use, but rather to be the core of the fetcher components described here.
+Fetches a byte of data from the Ethernet Controller registers via the [FPGA_Transceiver|Transceiver]. This unit creates yet another abstraction layer "in series" with the transceiver. The two step process of sending a request with all accompanying parameters and waiting for reply is now a matter of a single "call". The module does not latch the input data but puts it immediately on the Transceiver control bus. (This is safe since the Transceiver latches the input data and starts the conversation with the EC on the falling edge of its fast clock - a full 25 ns after the rising edge of the "Go" signal sent to <tt>getByte</tt>).
-=== Write Request (<tt>wrToAddr</tt>) ===
+== Write Request (<tt>wrToAddr</tt>) ==
-Sends a write request (R/W pin low) to transceiver at the specified address with the specified byte of data. The primary reason of this instruction "packaging" was to obscure the complexity of appropriate delays to ensure proper signal latching. The delayed version is currently commented out under the assumption of falling edge of clock latching of data by the Transceiver.
+Sends a write request (R/W pin low) to [FPGA_Transceiver|Transceiver] at the specified address with the specified byte of data. The module awaits the "Done" signal from the Transceiver and passes it to the calling module.
-=== 2-byte Write Request (<tt>wr2BtoAddr</tt>) ===
+== 2-byte Write Request (<tt>wr2BtoAddr</tt>) ==
-Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit buffer locations in random memory access. Only the address of the first register needs to be passed in.
+Coordinates write operations to two adjacent 1-byte registers in the Ethernet Controller chip. This is an essential abstraction because the controller often requires 16-bit exchanges especially when specifying 16-bit locations pointers in random memory access. Only the address of the first register is passed in. Naturally <tt>[[FPGA_Reusables#Write Request (<tt>wrToAddr</tt>)|wrToAddr]]</tt> is used for the individual byte writes.
-=== Auto-reader (<tt>AutoRd</tt>) ===
+== Auto-reader (<tt>AutoRd</tt>) ==
 Performs the same function as the Byte Fetcher (described above) but is hard-wired to address the RXAUTORD (0x01). This is convenient because the Ethernet Controller's AutoRead interface will be used extensively to parse through packets. <tt>AutoRd</tt> is in fact just a wrapper around <tt>GetByte</tt> passing through all signals accept the fixed address input.
-=== Random Access Write (<tt>RAwrToAddr</tt>) ===
+== Random Access Write (<tt>RAwrToAddr</tt>) ==
 Writing directly to Ethernet Controller RAM (not to be confused with the control registers) in random access mode requires more work. A 16-bit address needs to be passed in 8 bits at a time to appropriate control registers and the actual 8-bit data is sent on the third transaction. Because the buffer is sometimes loaded in sequentially, this unit is designed to just increment the address of the previous random access write if the passed in address has a '1' in the MSB. (This would never be a legal address, as it is out of range.) The calling module, therefore, does not need to store the current write location of the RAM. <tt>wr2BtoAddr</tt> and <tt>wrToAddr</tt> are very convenient for these three transactions.
-=== 2-byte Random Access Write (<tt>RAwr2BtoAddr</tt>) ===
+== 2-byte Random Access Write (<tt>RAwr2BtoAddr</tt>) ==
 Because the data values exchanged between the board and the PC range from 10 to 14 bit depth, zero padded 16-bit words will be used. So, to load this 2-byte word into the transfer buffer requires two random access writes.  This module packages this functionality by including two calls to <tt>RAwrToAddr</tt> with address increments and input data latching taken into account.