FPGA Reset - Revision history

Senderovich at 19:57, 20 October 2009

2009-10-20T19:57:17Z

2009-06-04T19:17:15Z

Ports

2008-06-03T01:00:25Z

2008-06-03T00:08:22Z

2008-06-03T00:07:56Z

2008-06-03T00:07:45Z

2008-06-03T00:07:19Z

2008-05-30T20:37:48Z

2008-05-29T19:05:42Z

2008-05-29T18:50:14Z

← Older revision		Revision as of 19:57, 20 October 2009
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	* ''dbShort'': [in] debug signal to bypass EC reset waiting periods		* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
		+

	== Programming Details of Rest_soft ==		== Programming Details of Rest_soft ==

@@ Line 45: / Line 45: @@
-[[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines
+[[FPGA_Registers#MAC_Address_Registers|MAC Address Register]] Control Lines
 * ''MACregs_En'': [out] register enable (write) signal
 * ''MACregs_A'': [out] byte address (4-bit)
@@ Line 60: / Line 60: @@
 * ''dbShort'': [in] debug signal to bypass EC reset waiting periods
 == Programming Details of Rest_soft ==

@@ Line 1: / Line 1: @@
-:''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and general discussion of FPGA design approach.''
+:''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''
 = (00X) Reset Modules =
@@ Line 16: / Line 16: @@
 |}
 === Ports ===
@@ Line 51: / Line 60: @@
 * ''dbShort'': [in] debug signal to bypass EC reset waiting periods

← Older revision		Revision as of 00:08, 3 June 2008
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−	:''See also [[Programming_the_Ethernet_controller]]'' for a survey of modules and general discussion of FPGA design approach.''	+	:''See also [[Programming_the_Ethernet_controller\|Programming the Ethernet Controller]]'' for a survey of modules and general discussion of FPGA design approach.''

	= (00X) Reset Modules =		= (00X) Reset Modules =

← Older revision		Revision as of 00:07, 3 June 2008
Line 1:		Line 1:
−	:''See also [[Programming_the_Ethernet_controller~~\|Programming the Ethernet Controller~~]]'' for a survey of modules and general discussion of FPGA design approach.''	+	:''See also [[Programming_the_Ethernet_controller]]'' for a survey of modules and general discussion of FPGA design approach.''

	= (00X) Reset Modules =		= (00X) Reset Modules =

@@ Line 44: / Line 44: @@
 * ''TxRx_Aout'': [out] EC control register address (8-bit)
 * ''TxRx_Dout'': [out] EC control register write value
-* ''TxRx_RiW'': [out]  active-high read, active-low write flag
+* ''TxRx_RiW'': [out] active-high read, active-low write flag
 * ''TxRx_Din'': [in] EC control register return value
 * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
 * ''dbShort'': [in] debug signal to bypass EC reset waiting periods

@@ Line 1: / Line 1: @@
-== (00X) Reset Modules ==
+= (00X) Reset Modules =
 The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)
-The control packets leading to states 00X pertaining to thes reset modules are:
+The control packets type bytes leading to states 00X pertaining to these reset modules are:
-{|
+{| class="wikitable" border="1" align="center" style="text-align:center" cellspacing="0" cellpadding="4"
-! Packet Type Byte || Hex value || Bin value || Description
+! colspan="3" | Packet Type Byte || colspan="2" | Effect on the FPGA
 |-
-| R || 0x52 || 0101 0010
+! Type || Hex || Bin || State || Description
 |-
-| "R'" || 0xD2 || '''1'''101 0010
+| R || 0x52 || 0101&nbsp;0010 || 000 || align="left" | "Reset_hard" instruction
 |}
 * ''Clk'': [in] clock