FPGA Reader - Revision history

Senderovich at 00:15, 3 June 2008

2008-06-03T00:15:33Z

Senderovich at 00:14, 3 June 2008

2008-06-03T00:14:47Z

Senderovich: /* Programming Details */

2008-06-02T22:16:09Z

Programming Details

Senderovich at 22:15, 2 June 2008

2008-06-02T22:15:43Z

Senderovich: /* Ports */

2008-06-02T20:44:31Z

Ports

Senderovich: /* Ports */

2008-06-02T20:44:22Z

Ports

Senderovich: /* Programming Details */

2008-06-02T20:43:26Z

Programming Details

Senderovich: /* Ports */

2008-06-02T20:21:41Z

Ports

Senderovich at 20:21, 2 June 2008

2008-06-02T20:21:19Z

Senderovich at 19:38, 2 June 2008

2008-06-02T19:38:43Z

← Older revision		Revision as of 00:15, 3 June 2008
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−	:''See also [[Programming_the_Ethernet_controller\|Programming the Ethernet Controller]]'' for a survey of modules and general discussion of FPGA design approach.''	+	:''See also [[Programming_the_Ethernet_controller\|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.''

	= (011) Read Packet =		= (011) Read Packet =

← Older revision		Revision as of 00:14, 3 June 2008
Line 1:		Line 1:
		+	:''See also [[Programming_the_Ethernet_controller\|Programming the Ethernet Controller]]'' for a survey of modules and general discussion of FPGA design approach.''
		+
	= (011) Read Packet =		= (011) Read Packet =

@@ Line 13: / Line 13: @@
 == Programming Details ==
-[[Image:PacketFormat.png|thumb|520px|Custom format of the packets exchanged between digital control boards and the PC.]]
+[[Image:PacketFormat.png|thumb|325px|Custom format of the packets exchanged between digital control boards and the PC.]]
 The module is implemented as a counter of bytes read with the auto-read interface of the Ethernet Controller chip (EC) starting from the beginning of the header. ''AutoRd'' module is instantiated and is pulsed on each counter click. Upon reading the 15th, the location is checked for match to the board slot's hardwired location (''LocStamp'' port listed below). Upon the 16th byte, the packet type is checked. Packet rejection (skipping in the receive buffer) if performed by writing "00000010" to RXCN (0x11) control register. (See the CP220x manual for more information.) ''wrToAddr'' module is instantiated and is pulsed by the Discard signal which may be turned high at any point of the selection process.

@@ Line 1: / Line 1: @@
 = (011) Read Packet =
 This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the [[Ethernet_packets|packet type]] is invalid. Otherwise it will yield control to the module relevant to the packet type. This selection is diagrammed in the adjacent figure.
 As implied in the diagram, packet types R and Q (Reset and Query respectively) do no carry any data for the FPGA: their role is to order reset or request feedback from the sensor chips. Soft Reset and Programmer, on the other hand require certain reset/configuration data and DAC voltage values respectively, so these packets are kept. (It becomes the responsibility of these modules to dismiss these packets when finished.)
@@ Line 11: / Line 12: @@
 == Programming Details ==
 The module is implemented as a counter of bytes read with the auto-read interface of the Ethernet Controller chip (EC) starting from the beginning of the header. ''AutoRd'' module is instantiated and is pulsed on each counter click. Upon reading the 15th, the location is checked for match to the board slot's hardwired location (''LocStamp'' port listed below). Upon the 16th byte, the packet type is checked. Packet rejection (skipping in the receive buffer) if performed by writing "00000010" to RXCN (0x11) control register. (See the CP220x manual for more information.) ''wrToAddr'' module is instantiated and is pulsed by the Discard signal which may be turned high at any point of the selection process.

← Older revision		Revision as of 20:44, 2 June 2008
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	* ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot		* ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot
		+

	[[FPGA_Transceiver\|Transceiver]] Control Lines		[[FPGA_Transceiver\|Transceiver]] Control Lines

@@ Line 27: / Line 27: @@
 * ''state_D'': [out] (3-bit) state register input
 * ''state_Q'': [in] (3-bit) state register output
 * ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot

@@ Line 11: / Line 11: @@
 == Programming Details ==
 Note that after stepping through the 14 bytes of the packet header and reading the first two bytes of the payload it leaves the receive (Rx) buffer pointer on the 17th byte (or 3rd byte of payload). The Soft Reset and Programmer modules can continue reading with the auto-read interface to access the data relevant to them.
@@ Line 26: / Line 28: @@
 * ''state_Q'': [in] (3-bit) state register output
 [[FPGA_Transceiver|Transceiver]] Control Lines
@@ Line 33: / Line 36: @@
 * ''TxRx_Dout'': [out] EC control register write value
 * ''TxRx_Din'': [in] EC control register return value
-* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
+* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]

← Older revision		Revision as of 20:21, 2 June 2008
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	* ''Clk'': [in] clock		* ''Clk'': [in] clock
−	* ''/Rst'': [in] asynchronous~~, active-low~~ reset	+	* ''Rst'': [in] asynchronous reset

@@ Line 1: / Line 1: @@
 = (011) Read Packet =
-This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the packet type is invalid. Otherwise it will yield control to the module relevant to the packet type.
+This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the [[Ethernet_packets|packet type]] is invalid. Otherwise it will yield control to the module relevant to the packet type. This selection is diagrammed in the adjacent figure.
-[[Image:ReaderProcess.png|frame|width:236px]]
+[[Image:ReaderProcess.png|thumb|236px|Process flow of the Reader module. "my_Loc" represents either the constant 8-bit value hard-coded into the slot to which the digital board is attached or the wild card: 0xFF]]
-Block 011 is the only block with switching between following states.  Its first task is to load the MAC data of the packet.  If filtering inside of the FPGA is required, this block is responsible for it.  The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet).  If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010.  The MAC filter would be the first substate.
+As implied in the diagram, packet types R and Q (Reset and Query respectively) do no carry any data for the FPGA: their role is to order reset or request feedback from the sensor chips. Soft Reset and Programmer, on the other hand require certain reset/configuration data and DAC voltage values respectively, so these packets are kept. (It becomes the responsibility of these modules to dismiss these packets when finished.)
-After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary).  This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
+Instead of implementing MAC address filtering, necessitating a lookup table of MAC address to Energy channel group, it was seen as more convenient to include an 8-bit bus into the slots for the digital boards, each hard-wired to hold a unique location value. Knowing the number of energy channels controlled on each board, the packet addressing is straightforward. Packet filtering is also made easy for the Reader: it requires a simple 8-bit comparison between the hard-coded value and that in the first byte of the packet payload.
-Stepping through the 14 bytes of the packet header and reading the first two bytes of the payload it leaves the receive (Rx) buffer pointer on the 17th byte (or 3rd byte of payload).
+== Programming Details ==
-internal signals
+=== Ports ===
-blocks
+* ''Clk'': [in] clock
-* '''MAC Filter'''
+* ''/Rst'': [in] asynchronous, active-low reset
-** This block checks that the MAC address in the packet destination field is the same as the MAC address of the board.  If not the packet is discarded, if so then the MAC data (destination and source MAC address, packet length) are discarded and processing continues.
-** inputs
-*** ''Clk'': clock
+[[FPGA_Registers#State_Register|State Register]] Control Lines
-*** ''/Rst'': asynchronous, active-low reset
+* ''state_En'': [out] state register enable (write) signal
-*** ''Go'': pulse to begin
+* ''state_D'': [out] (3-bit) state register input
-*** - transceiver control lines -
+* ''state_Q'': [in] (3-bit) state register output
-** outputs
-*** ''Discard'': pulse to State Advance to discard packet and return to 010
-*** ''Continue'': pulse to Switch to continue processing
+[[FPGA_Transceiver|Transceiver]] Control Lines
-*** - transceiver control lines -
+* ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte
-* '''Switch'''
+* ''TxRx_RiW'': [out] active-high read, active-low write flag
-** This block reads the first data byte of the packet and uses it as a switch to direct the state machine to the appropriate next step.
+* ''TxRx_Aout'': [out] EC control register address (8-bit)
-** inputs
+* ''TxRx_Dout'': [out] EC control register write value
-*** ''Clk'': clock
+* ''TxRx_Din'': [in] EC control register return value
-*** ''/Rst'': asynchronous, active-low reset
+* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].