FPGA Programmer - Revision history

Senderovich at 06:22, 5 November 2009

2009-11-05T06:22:59Z

Senderovich at 17:36, 3 June 2008

2008-06-03T17:36:13Z

Senderovich: /* Programming Details */

2008-06-03T17:10:45Z

Programming Details

Senderovich at 16:40, 3 June 2008

2008-06-03T16:40:23Z

Senderovich at 16:26, 3 June 2008

2008-06-03T16:26:42Z

Senderovich at 19:04, 16 May 2008

2008-05-16T19:04:57Z

New page

== (110) Program DAC ==

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
* '''Discarder'''
** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

@@ Line 3: / Line 3: @@
 The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values.
-The mask selects which channels must be altered. Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 0  and the LSB of the fourth byte will be channel 31.  Thus, if only channels 14 through 26 are to be programmed, the mask would contain:
+The mask selects which channels must be altered. Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location.  The MSB of the first byte will be channel 0  and the LSB of the fourth byte will be channel 31.  Thus, if only channels 5 through 17 are to be programmed, the mask would contain:
 {| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
 ! First data byte
@@ Line 23: / Line 23: @@
-The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. The first stage involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows immediately after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the [[Programming_the_DAC|DAC Controller]] for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered or to avoid writing to unused channels of the DAC, the mask must contain 0's for the corresponding bits. The [[FPGA_Registers#DAC Register|DAC Register]] is pulsed simulataneously with the DAC controller to record the programmed value. The will later be sent back to the PC for confirmation. (No feedback from the DAC chip itself is possible. Some channels may be sampled by the ADC if necessary.)
+The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. The first stage involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows immediately after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the [[Programming_the_DAC|DAC Controller]] for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered the mask must contain 0's for the corresponding bits. If a requested value exceeds the voltage level hardwired into the FPGA firmware, this maximum value is set instead of that requested by in the P-packet. The responding D-packet will reflect this correction.

@@ Line 3: / Line 3: @@
 The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values.
 == Programming Details ==
-[[Image:P-packetPayload.png|thumb|P-packet Format]]
+[[Image:P-packetPayload.png|frame|P-packet Format]]
@@ Line 18: / Line 32: @@
-Write signals to the [[Programming_the_DAC|DAC Controller]]
+Write signals to the [[Programming_the_DAC|DAC Controller]] and [[FPGA_Registers#DAC Register|DAC Register]]
 * ''DAC_iGo'': [out] active-low "Go" signal
 * ''DAC_Addr'': [out] 5-bit DAC channel address
-[the 14-bit DAC value is synonymous with that passed to the DAC register. See below.]
+* ''DAC_D'': [out] 14-bit voltage value for the register and DAC Controller
@@ Line 28: / Line 44: @@
 * ''state_D'': [out] (3-bit) state register input
 * ''state_Q'': [in] (3-bit) state register output

← Older revision		Revision as of 17:10, 3 June 2008
Line 6:		Line 6:
	== Programming Details ==		== Programming Details ==

−	The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. ~~In the~~ first stage, involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows ~~immediate~~ after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the [[Programming_the_DAC\|DAC Controller]] for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered or to avoid writing to unused channels of the DAC, the mask must contain 0's for the corresponding bits. The [[FPGA_Registers#DAC Register\|DAC Register]] is pulsed simulataneously with the DAC controller to record the programmed value. The will later be sent back to the PC for confirmation. (No feedback from the DAC chip itself is possible. Some channels may be sampled by the ADC if necessary.)	+	[[Image:P-packetPayload.png\|thumb\|P-packet Format]]
		+
		+
		+	The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. The first stage involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows immediately after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the [[Programming_the_DAC\|DAC Controller]] for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered or to avoid writing to unused channels of the DAC, the mask must contain 0's for the corresponding bits. The [[FPGA_Registers#DAC Register\|DAC Register]] is pulsed simulataneously with the DAC controller to record the programmed value. The will later be sent back to the PC for confirmation. (No feedback from the DAC chip itself is possible. Some channels may be sampled by the ADC if necessary.)

← Older revision		Revision as of 16:40, 3 June 2008
Line 6:		Line 6:
	== Programming Details ==		== Programming Details ==

		+	The Programmer is one of the more complex modules. There are two stages involved in its process: mask and data. In the first stage, involves reading and storing the 4-byte mask (32-bits corresponding to 32 channels of the DAC), which follows immediate after the location and type bytes of the P-packet payload. Then the Programmer steps through the rest of the P-packet in 2-byte words, each containing the 14-bit DAC voltage, ordering write operations via the [[Programming_the_DAC\|DAC Controller]] for each one. The packet is expected to have all 32 values in ascending order of channels. For any channels that need not be altered or to avoid writing to unused channels of the DAC, the mask must contain 0's for the corresponding bits. The [[FPGA_Registers#DAC Register\|DAC Register]] is pulsed simulataneously with the DAC controller to record the programmed value. The will later be sent back to the PC for confirmation. (No feedback from the DAC chip itself is possible. Some channels may be sampled by the ADC if necessary.)

@@ Line 1: / Line 1: @@
-== (110) Program DAC ==
+== (110) DAC Programmer ==
-This block will have a substate to obtain the programming mask.  It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC.  A mux may be needed to select the appropriate bit from the programming mask.  It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet.  Then it transitions to state 111.
+The DAC Programmer assigns DAC voltages according to the mask and values listed in the P-packet payload. The module always passes control to the Transmitter to send a D-packet, confirming the requested values.
-internal signals
+== Programming Details ==
-blocks
-* '''Mask Fetcher'''
-** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
+=== Ports ===
-** inputs
-*** ''Clk'': clock
+* ''Clk'': [in] clock
-*** ''/Rst'': asynchronous, active-low reset
+* ''Rst'': [in] asynchronous reset
-*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
-*** ''TxRx_D'': 8-bit data bus from transceiver
-*** ''TxRx_Done'': ''Done'' signal from transceiver
+Write signals to the [[Programming_the_DAC|DAC Controller]]
-** outputs
+* ''DAC_iGo'': [out] active-low "Go" signal
-*** ''TxRx_Go'': ''Go'' input on transceiver
+* ''DAC_Addr'': [out] 5-bit DAC channel address
-*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
+[the 14-bit DAC value is synonymous with that passed to the DAC register. See below.]
-*** ''TxRx_A'': ''A_in'' bus on transceiver
-*** ''Mask'': 32/24/16-bit readout of programming mask
-*** ''Done'': pulse to signal that mask has been obtained
+[[FPGA_Registers#State_Register|State Register]] Control Lines
-* '''Programmer'''
+* ''state_En'': [out] state register enable (write) signal
-** Programs the DAC.  Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0.  Also writes the value to the internal DAC value storage registers (or Flash memory or other).
+* ''state_D'': [out] (3-bit) state register input
-** inputs
+* ''state_Q'': [in] (3-bit) state register output
-*** ''Clk'': clock
-*** ''/Rst'': asynchronous, active-low reset
-*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
+[[FPGA_Registers#DAC Register|DAC Register]] control lines
-*** ''TxRx_D'': ''D_out'' bus on transceiver
+* ''DACReg_En'': [out] ;
-*** ''TxRx_Done'': ''Done'' signal on transceiver
+* ''--DACReg_Addr'': [out] _VECTOR (4 downto 0);
-** outputs
+* ''DACReg_D'': [out] 14-bit voltage value for the register and DAC Controller
-*** - DAC control lines -
+* ''DACReg_Q'': [in] _VECTOR (15 downto 0);
-*** ''TxRx_Go'': ''Go'' signal on transceiver
-*** ''TxRx_R/W'': ''R/W'' signal on transceiver
-*** ''TxRx_A'': ''A_in'' bus on transceiver
+[[FPGA_Transceiver|Transceiver]] Control Lines
-*** ''Sel'': 5/5/4-bit select bus to internal registers
+* ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte
-*** ''Data'': 32/24/16-bit data bus to internal registers
+* ''TxRx_RiW'': [out] active-high read, active-low write flag
-*** ''Done'': pulse to signal completion
+* ''TxRx_Aout'': [out] EC control register address (8-bit)
-* '''Discarder'''
+* ''TxRx_Din'': [in] EC control register return value
-** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
+* ''TxRx_Dout'': [out] EC control register write value
-** inputs
+* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]]