Amplifier board debugging notes - Revision history

Senderovich at 15:31, 13 September 2011

2011-09-13T15:31:59Z

Senderovich: /* Change of reference for summing circuit input stage DC level */

2010-09-30T16:31:35Z

Change of reference for summing circuit input stage DC level

Senderovich: /* Change of reference for summing circuit input stage DC level */

2010-09-30T16:29:16Z

Change of reference for summing circuit input stage DC level

Senderovich: /* Change of reference for summing circuit input stage DC level */

2010-09-30T16:28:44Z

Change of reference for summing circuit input stage DC level

Senderovich: /* Change of reference for summing circuit CD level */

2010-09-30T16:12:55Z

Change of reference for summing circuit CD level

Senderovich at 01:48, 29 September 2010

2010-09-29T01:48:42Z

Senderovich: /* Thermistor/resistor tolerance */

2010-09-29T01:39:01Z

Thermistor/resistor tolerance

Senderovich at 01:09, 6 July 2010

2010-07-06T01:09:11Z

Senderovich at 16:26, 31 March 2010

2010-03-31T16:26:48Z

Senderovich at 16:21, 31 March 2010

2010-03-31T16:21:35Z

← Older revision		Revision as of 15:31, 13 September 2011
Line 1:		Line 1:
	This page contains a list of all currently known problems with the amplifier board and the solutions implemented		This page contains a list of all currently known problems with the amplifier board and the solutions implemented
		+
		+	= Issue List =
		+
		+	* check that the summing circuit is up to date
		+	* finalize DC plane "fingers"
		+	* settle on switch circuit design
		+	* check voltage references
		+	* check impedance matching, where relevant (possible on internal layers?)
		+	* ensure sufficient bypass
		+
		+
		+
		+
		+	= Bug List =

	== Improper DC levels from voltage regulators ==		== Improper DC levels from voltage regulators ==

@@ Line 24: / Line 24: @@
 The adjacent diagram shows the necessary circuit. The component values are set as follows.
 * Recommended values for V<sub>cc</sub> - V<sub>B4</sub> = 0.9V - {R1,R2} = {30k&Omega;,100k&Omega;}
-* Good value for I<sub>k</sub> is 2mA. Current through R1, R2 is negligible, as is the current going to the load (6 summers x 10uA base current) This I<sub>k</sub> ~ I, so R ~ 2k&Omega; (but anywhere 1-5k&Omega; works)
+* Good value for I<sub>k</sub> is 2mA. Current through R1, R2 is negligible, as is the current going to the load (6 summers x 10uA base current) Thus I<sub>k</sub> ~ I, so R ~ 2k&Omega; (but anywhere 1-5k&Omega; works)
 == Wrong voltage on R<sub>C</sub>/R<sub>D</sub> junction ==

@@ Line 23: / Line 23: @@
 The adjacent diagram shows the necessary circuit. The component values are set as follows.
-* Recommended values for V<sub>cc</sub>-V<sub>B4</sub> = 0.9V - {R1,R2}={30k&Omega;,100k&Omega;}
+* Recommended values for V<sub>cc</sub> - V<sub>B4</sub> = 0.9V - {R1,R2} = {30k&Omega;,100k&Omega;}
-* Good value for I<sub>k</sub> 2mA. Current through R1, R2 is negligible, as is the current going to the load (6 summers x 10uA base current) This I<sub>k</sub> ~ I, so R ~ 2k&Omega; (but anywhere 1-5k&Omega; works)
+* Good value for I<sub>k</sub> is 2mA. Current through R1, R2 is negligible, as is the current going to the load (6 summers x 10uA base current) This I<sub>k</sub> ~ I, so R ~ 2k&Omega; (but anywhere 1-5k&Omega; works)
 == Wrong voltage on R<sub>C</sub>/R<sub>D</sub> junction ==

@@ Line 17: / Line 17: @@
 == Change of reference for summing circuit input stage DC level ==
 The new PNP input stage of the summing circuit, in order to be placed far from cutoff and saturation, is very sensitive to its emitter current, which, with RE=154&Omega; requires transistor base control on the order of 10mV. Basically, we need the set the base for the desired emitter voltage and accounting for the diode drop ''referencing Vcc, not ground, as it was with NPN''. The shunt voltage regulators used so far can be employed for this, but the ~0.9V offset from Vcc cannot be done with most regulators as they use a double diode drop - 1.24V as internal reference and allow settings above this value. A reference NCP100 SNT 1G (On semiconductors) has been chosen because of it's lower possible settings, making reference to just one diode drop: 0.698V
-The adjacent diagram shows the necessary circuit.
+The adjacent diagram shows the necessary circuit. The component values are set as follows.
 == Wrong voltage on R<sub>C</sub>/R<sub>D</sub> junction ==

@@ Line 16: / Line 16: @@
-== Change of reference for summing circuit CD level ==
+== Change of reference for summing circuit input stage DC level ==
 The new PNP input stage of the summing circuit, in order to be placed far from cutoff and saturation, is very sensitive to its emitter current, which, with RE=154&Omega; requires transistor base control on the order of 10mV. Basically, we need the set the base for the desired emitter voltage and accounting for the diode drop ''referencing Vcc, not ground, as it was with NPN''. The shunt voltage regulators used so far can be employed for this, but the ~0.9V offset from Vcc cannot be done with most regulators as they use a double diode drop - 1.24V as internal reference and allow settings above this value. A reference NCP100 SNT 1G (On semiconductors) has been chosen because of it's lower possible settings, making reference to just one diode drop: 0.698V
 The adjacent diagram shows the necessary circuit.
 == Wrong voltage on R<sub>C</sub>/R<sub>D</sub> junction ==

← Older revision		Revision as of 01:48, 29 September 2010
Line 14:		Line 14:
	* the ICs were rotated such that 2 pins (Vref and Gnd) are bonded to their nets. The loose Vz pin was connected via wire to its proper proper net.		* the ICs were rotated such that 2 pins (Vref and Gnd) are bonded to their nets. The loose Vz pin was connected via wire to its proper proper net.
	* '''modifications of the PCB layout is pending'''		* '''modifications of the PCB layout is pending'''
		+
		+
		+	== Change of reference for summing circuit CD level ==
		+	The new PNP input stage of the summing circuit, in order to be placed far from cutoff and saturation, is very sensitive to its emitter current, which, with RE=154Ω requires transistor base control on the order of 10mV. Basically, we need the set the base for the desired emitter voltage and accounting for the diode drop ''referencing Vcc, not ground, as it was with NPN''. The shunt voltage regulators used so far can be employed for this, but the ~0.9V offset from Vcc cannot be done with most regulators as they use a double diode drop - 1.24V as internal reference and allow settings above this value. A reference NCP100 SNT 1G (On semiconductors) has been chosen because of it's lower possible settings, making reference to just one diode drop: 0.698V
		+
		+	The adjacent diagram shows the necessary circuit.

← Older revision		Revision as of 01:39, 29 September 2010
Line 60:		Line 60:
	* Non implemented on prototype board. Suggestion: review whether this tolerance is sufficient at operating temperatures.		* Non implemented on prototype board. Suggestion: review whether this tolerance is sufficient at operating temperatures.
	* '''consideration of the revision and modifications of the PCB layout are pending'''		* '''consideration of the revision and modifications of the PCB layout are pending'''
		+
		+	=== Update ===
		+	Readout and interpretation of the temperature from this circuit results in about 5degC error! Interpretation:
		+	* 5% tolerance may contribute a few degrees (though replacing with 1% 100k resistor didn't move the accuracy significantly)
		+	* There is an ambiguity in the B parameter for this NTC thermistor: the table given in the manual does not seem to agree with the stated value of B of this device. However, this effects the reading on the scale of a 0.1deg
		+	* few mV drop in the voltage may be occurring between the thermistor pin and ADC chip. Path resistance can be calculated and taken into account. (Significance to be verified)

← Older revision		Revision as of 01:09, 6 July 2010
Line 50:		Line 50:
	* The purchases LEMO receptacle pins were filed to fit the holes of the prototype board.		* The purchases LEMO receptacle pins were filed to fit the holes of the prototype board.
	* '''modifications of the PCB layout is pending'''		* '''modifications of the PCB layout is pending'''
		+
		+
		+	== Thermistor/resistor tolerance ==
		+
		+	=== Description ===
		+	The 100k resistor and thermistor picked for the voltage divider (used by control board/software to determine thermistor's reading) is of 5% tolerance
		+
		+	=== Solution ===
		+	* Non implemented on prototype board. Suggestion: review whether this tolerance is sufficient at operating temperatures.
		+	* '''consideration of the revision and modifications of the PCB layout are pending'''

@@ Line 17: / Line 17: @@
 == Wrong voltage on R<sub>C</sub>/R<sub>D</sub> junction ==
 === Description ===
@@ Line 31: / Line 30: @@
 == FET switch compatibility ==
 === Description ===
 The FET switch BF1108 was not available in our market. Only its mirror package variant BF1108R could be procured.
@@ Line 36: / Line 36: @@
 === Solution ===
 * ''Temporary solution'': The adaptation of the board for the BF1108R is shown in the adjacent figure. The IC is positioned in the shown orientation and its pins (pads) linked as shown.
 * '''modifications of the PCB layout is pending'''

@@ Line 2: / Line 2: @@
 == Improper DC levels from voltage regulators ==
 === Description ===
@@ Line 7: / Line 8: @@
 === Cause ===
 The pads for pins Gnd and Vz of the voltage regulators were reversed. The proper assignment of pins is shown in the adjacent figure.
@@ Line 17: / Line 17: @@
 == Wrong voltage on R<sub>C</sub>/R<sub>D</sub> junction ==
 === Description ===
 A voltage of 2.75&nbsp;V was measured on the junction between R<sub>C</sub> and R<sub>D</sub> resistors, instead of 2.25&nbsp;