UConn PAN - User contributions [en]

Programming the FPGA

2007-07-20T19:53:57Z

Krueger:

[[Image:Spartan.jpg|right]]

The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in [[VHDL_tutorial|VHDL]]. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.

== Open questions ==

Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
* What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
* Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component. This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip. ''Work in progress'': see [[Reset and Initialization]].
* Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
* A core VHDL module is needed to tie all the components together. The Ethernet controller module may take on the role of FPGA core.

== Component code ==

* [[Programming the DAC]]
* [[Programming the SPI]]
* [[Programming the Ethernet controller]]
* [[Reset and Initialization]]

Design and prototyping of SiPM electronics

2007-07-20T19:52:08Z

Krueger:

This page is a work in progress. More information will be added as the project progresses.

== Internal Links ==

=== Analog amplifier ===

* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.

=== Digital control ===

* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.

==== Programming our FPGA ====

* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the SPI]] - discussion of the new hybrid module that controls both the ADC and the temperature sensor over a single SPI bus.
*** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
*** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.

==== VHDL in general ====

* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** <S>Integrate with/''combine into'' existing modules</S> ''update'': integrated into [[Programming_the_Ethernet_controller#.28000.29_Reset_Cycle|Ethernet module]]
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Design and prototyping of SiPM electronics

2007-07-20T19:46:46Z

Krueger: /* To-do list */

__NOTOC__
This page is a work in progress. More information will be added as the project progresses.

== Links ==

=== Analog amplifier ===

* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.

=== Digital control ===

* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.

==== Programming our FPGA ====

* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the SPI]] - discussion of the new hybrid module that controls both the ADC and the temperature sensor over a single SPI bus.
*** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
*** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.

==== VHDL in general ====

* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** <S>Integrate with/''combine into'' existing modules</S> ''update'': integrated into [[Programming_the_Ethernet_controller#.28000.29_Reset_Cycle|Ethernet module]]
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Design and prototyping of SiPM electronics

2007-07-20T19:43:55Z

Krueger: /* To-do list */

__NOTOC__
This page is a work in progress. More information will be added as the project progresses.

== Links ==

=== Analog amplifier ===

* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.

=== Digital control ===

* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.

==== Programming our FPGA ====

* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the SPI]] - discussion of the new hybrid module that controls both the ADC and the temperature sensor over a single SPI bus.
*** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
*** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.

==== VHDL in general ====

* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** <S>Integrate with/''combine into'' existing modules</S> ''update'': integrated into Ethernet module
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Design and prototyping of SiPM electronics

2007-07-20T19:43:41Z

Krueger: /* To-do list */

__NOTOC__
This page is a work in progress. More information will be added as the project progresses.

== Links ==

=== Analog amplifier ===

* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.

=== Digital control ===

* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.

==== Programming our FPGA ====

* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the SPI]] - discussion of the new hybrid module that controls both the ADC and the temperature sensor over a single SPI bus.
*** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
*** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.

==== VHDL in general ====

* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** <S>Integrate with/''combine into'' existing modules</S> Update: integrated into Ethernet module
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Design and prototyping of SiPM electronics

2007-07-20T19:33:09Z

Krueger:

__NOTOC__
This page is a work in progress. More information will be added as the project progresses.

== Links ==

=== Analog amplifier ===

* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.

=== Digital control ===

* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.

==== Programming our FPGA ====

* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the SPI]] - discussion of the new hybrid module that controls both the ADC and the temperature sensor over a single SPI bus.
*** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
*** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.

==== VHDL in general ====

* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** Integrate with/''combine into'' existing modules
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Programming the SPI

2007-07-20T19:28:24Z

Krueger:

'''This page discusses a project currently under development. Please be aware that information on this page may change as the project progresses.'''

This module aims to merge the ADC and temperature sensor modules into a single module. Both modules communicate over a shared SPI-like bus, and there are many structural and functional similarities between the two. However, this is a partially completed project. The current VHDL files (which are mostly written but need to be tested) can be found at:
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/SPI_VHDL.zip SPI Module].
The subprojects (i.e. earlier versions of the separate ADC and temperature sensor modules) can be found at:
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip ADC Module]
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/Temp_VHDL.zip Temperature Sensor Module]

Programming the SPI

2007-07-20T19:27:51Z

Krueger:

'''This page discusses a project currently under development. Please be aware that information on this page may change as the project progresses.'''

This module aims to merge the ADC and temperature sensor modules into a single module. Both modules communicate over a shared SPI-like bus, and there are many structural and functional similarities between the two. However, this is a partially completed project. The current VHDL files (which are mostly written but need to be tested) can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/SPI_VHDL.zip here]. The subprojects (i.e. earlier versions of the separate ADC and temperature sensor modules) can be found at:
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip ADC Module]
* [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/Temp_VHDL.zip Temperature Sensor Module]

Design and prototyping of SiPM electronics

2007-07-20T19:18:03Z

Krueger:

__NOTOC__
This page is a work in progress. More information will be added as the project progresses.

== Links ==

=== Analog amplifier ===
* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.
=== Digital control ===
* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.
* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the SPI]] - discussion of the new hybrid module that controls both the ADC and the temperature sensor over a single SPI bus.
*** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
*** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.
* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** Integrate with/''combine into'' existing modules
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Programming the Ethernet controller

2007-07-20T18:41:35Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''

'''A discussion of the Multiplexed Intel bus format should be placed here.''' Until this section is complete, refer to the CP2200/1 data sheet for information.

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion. The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A 16-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the only block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* - transceiver control lines -

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''MAC Filter'''
** This block checks that the MAC address in the packet destination field is the same as the MAC address of the board. If not the packet is discarded, if so then the MAC data (destination and source MAC address, packet length) are discarded and processing continues.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin
*** - transceiver control lines -
** outputs
*** ''Discard'': pulse to State Advance to discard packet and return to 010
*** ''Continue'': pulse to Switch to continue processing
*** - transceiver control lines -
* '''Switch'''
** This block reads the first data byte of the packet and uses it as a switch to direct the state machine to the appropriate next step.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin
*** - transceiver control lines -
** outputs
*** ''Discard'': pulse to State Advance to discard packet and return to 010
*** ''Reset_000'': pulse to State Advance to discard packet and go to 000
*** ''Query'': pulse to State Advance to discard packet and go to 100
*** ''Program'': pulse to State Advance to keep packet and go to 110
*** - transceiver control lines -
* '''State Advance'''
** This block has several ''Go'' lines and based on which is pulsed the next state is set up by loading a new state value into the state register. It also discards packets other than "P".
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Discard'': pulse to discard packet and return to 010
*** ''Reset_000'': pulse to discard packet and go to 000
*** ''Query'': pulse to discard packet and go to 100
*** ''Program'': pulse to keep packet and go to 110
*** - transceiver control lines -
** outputs
*** ''Done'': pulse to signal completion; connects to state register enable
*** ''New_St'': new state to load to state register; goes to 000, 010, 100, or 110 when ''Done'' is high depending on switching
*** - transceiver control lines -

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
* '''Discarder'''
** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T20:27:21Z

Krueger: /* Interface */

== Interface ==

:''See also: [[Ethernet packets]]''

'''A discussion of the Multiplexed Intel bus format should be placed here.''' Until this section is complete, refer to the CP2200/1 data sheet for information.

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion. The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A 16-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the only block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
* '''Discarder'''
** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T20:26:22Z

Krueger: /* Non-State Components */

== Interface ==

:''See also: [[Ethernet packets]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion. The transceiver is intended to function on the Multiplexed Intel bus format to communicate with the CP2200/1.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A 16-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the only block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
* '''Discarder'''
** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T20:25:24Z

Krueger: /* (110) Program DAC */

== Interface ==

:''See also: [[Ethernet packets]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A 16-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the only block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
* '''Discarder'''
** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T20:22:22Z

Krueger: /* (011) Read Packet */

== Interface ==

:''See also: [[Ethernet packets]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A 16-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the only block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T20:21:14Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A 16-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 16-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Temp Loader'''
** This block reads the temperature value from the internal registers and loads it to the transmit buffer.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Go'' internal signal of block 101
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''ADC Loader'''
** This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Temp Loader
*** ''D_in'': 16-bit data bus from internal registers
*** ''TxRx_Done'': ''Done'' signal from transceiver
** ouputs
*** ''Sel'': 3-bit select bus for internal registers
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Padder'''
** This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of ADC Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** This block tells the CP2200/1 to send the completed packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Padder
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T19:46:39Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A ten-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''
*** ''New_St'': new state value to load into state register; goes to 011 when ''Done'' is high

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 12-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Loader'''
** Loads the DAC values into a packet in the transmission buffer of the CP2200/1. Loops through all values and loads them in order (channel zero to channel thirty-one).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin loading a packet
*** ''TxRx_Done'': ''Done'' signal on transceiver
*** ''Data'': 14-bit data bus from internal registers
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
* '''Sender'''
** Tells CP2200/1 to send the packet
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, connected to ''Done'' signal from Loader
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_RW'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''TxRx_D'': ''D_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high

Programming the Ethernet controller

2007-07-19T19:36:03Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet_packets#The_query_cycle|Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet_packets#The_programming_cycle|Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

=== Non-State Components ===

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus
* '''temperature register'''
** A ten-bit register to store the most recent temperature data.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': ten-bit data-in bus
** outputs
*** ''Q'': ten-bit data-out bus
* '''ADC registers'''
** A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 3-bit select bus
*** ''D'': 12-bit data-in bus
** outputs
*** ''Q'': 12-bit data-out bus; outputs data of register chosen by S bus
* '''DAC registers'''
** A set of 32/24/16 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''S'': 5/5/4-bit select bus
*** ''D'': 14-bit data-in bus
** outputs
*** ''Q'': 14-bit data-out bus; outputs data of register chosen by S bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Transmitter'''
** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin sending
*** ''Inc'': ''Done'' signal from transceiver; initiates next sending
** outputs
*** ''TxRx_A'': ''A_in'' signal to transceiver
*** ''TxRx_D'': ''D_in'' signal to transceiver
*** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero)
*** ''TxRx_Go'': ''Go'' signal to transceiver
*** ''Done'': pulses for one cycle; connects to state register as an enable line
*** ''New_St'': new state to load into state register; tied to 010

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''ADC Poll'''
** Updates values stored in the FPGA from the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All ADC control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''Go'' pulse
*** ''En'': enable line for writing to the internal registers
*** ''Sel'': 3-bit select bus to specify which ADC channel data is available
*** ''Data'': 12-bit data bus to carry data to FPGA internal registers
* '''Temp Poll'''
** Updates value stored in the FPGA from the temperature sensor.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': go pulse to begin
** outputs
*** - All temperature sensor control lines -
*** ''En'': enable line for writing to the internal register
*** ''Data'': 10-bit data bus to carry data to FPGA internal registers
* '''Coordinator'''
** Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Done'': high when ADC is done polling
** outputs
*** ''Done'': when ''A_Done'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
**: Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.
*** ''New_St'': new state to be written to the state register; goes to 101 while ''Done'' is high

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Mask Fetcher'''
** This block reads the programming mask, contained in the second data byte (first remaining byte) through the 5th/4th/3rd byte (4th/3rd/2nd remaining byte), and saves it into a 32/24/16-bit register.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin, comes from ''Go'' internal signal of block 110
*** ''TxRx_D'': 8-bit data bus from transceiver
*** ''TxRx_Done'': ''Done'' signal from transceiver
** outputs
*** ''TxRx_Go'': ''Go'' input on transceiver
*** ''TxRx_R/W'': ''R/W'' input on transceiver; tied to read (one)
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Mask'': 32/24/16-bit readout of programming mask
*** ''Done'': pulse to signal that mask has been obtained
* '''Programmer'''
** Programs the DAC. Loops 32/24/16 times, obtaining the next byte from the CP2200/1 buffer, checking the mask, programming the DAC if the mask is 1 or skipping if the mask is 0. Also writes the value to the internal DAC value storage registers (or Flash memory or other).
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Mask Fetcher
*** ''TxRx_D'': ''D_out'' bus on transceiver
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** - DAC control lines -
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; tied to 111

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

Programming the Ethernet controller

2007-07-19T18:49:16Z

Krueger:

Programming the Ethernet controller

2007-07-19T18:13:21Z

Krueger: /* (001) Transmit "I" */

Programming the Ethernet controller

2007-07-19T16:34:52Z

Krueger: /* (100) Poll Status */

Programming the Ethernet controller

2007-07-19T16:33:47Z

Krueger: /* Non-State Components */

Programming the Ethernet controller

2007-07-19T16:30:30Z

Krueger: /* (100) Poll Status */

Programming the Ethernet controller

2007-07-19T16:24:41Z

Krueger: /* (100) Poll Status */

Programming the Ethernet controller

2007-07-19T16:21:14Z

Krueger: /* (100) Poll Status */

Programming the Ethernet controller

2007-07-19T15:57:15Z

Krueger: /* (001) Transmit "I" */

Programming the Ethernet controller

2007-07-19T15:55:42Z

Krueger: /* = Non-State Components */

Programming the Ethernet controller

2007-07-19T15:55:35Z

Krueger: /* = */

Programming the Ethernet controller

2007-07-19T15:55:25Z

Krueger: /* Controller */

Programming the Ethernet controller

2007-07-19T15:45:49Z

Krueger:

Programming the Ethernet controller

2007-07-19T15:41:46Z

Krueger: /* Interface */

Design and prototyping of SiPM electronics

2007-07-19T15:41:22Z

Krueger:

__NOTOC__
This page is a work in progress. More information will be added as the project progresses.

== Links ==

=== Analog amplifier ===
* [[SiPM Amplifier]] - analog amplifier circuit supplied by [http://www.photonique.ch/ Photonique] for use with the SiPMs.
* [[MATLAB amplifier in detail]] - more information regarding the implementation of the MATLAB-based simulation of the amplifier circuit.
=== Digital control ===
* [[SiPM digital control board]] - digital PCB for controlling the SiPMs.
* [[Programming the FPGA]] - central page for programming the FPGA.
** [[Programming the DAC]] - discussion of the design for the DAC.
** [[Programming the temperature sensor]] - discussion of the design for the temperature sensor.
** [[Programming the ADC]] - discussion of the design for the ADC.
** [[Programming the Ethernet controller]] - discussion of the design for the Ethernet controller.
*** [[Ethernet packets]] - a detail of the packets we intend to use on our network.
** [[Reset and Initialization]] - discussion of the design for the reset and initialization core.
* [[VHDL tutorial]] - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.
** [[VHDL: Where to start]] - section one of the tutorial, focusing on preparing your design for coding.
** [[VHDL: Enter the code monkey]] - section two of the tutorial, focusing on outlining the framework of your code.
** [[VHDL: The real code]] - section three of the tutorial, focusing on coding the body of your design.
** [[VHDL: Xilinx ISE]] - section four of the tutorial, focusing on using the development environment.

== To-do list ==

* Upload [[Programming the ADC|ADC module]] block diagrams
* Combine [[Programming the ADC|ADC]] & [[Programming the temperature sensor|temperature sensor]] into single "SPI" module
* [[Reset and Initialization|Reset module]]
** Execute on startup
** Execute on command
** Integrate with/''combine into'' existing modules
* Complete [[Programming the Ethernet controller|Ethernet controller module]]
* Integrate all modules
* Determine size of FPGA
* Design or purchase connector to bus board
* Purchase all components (including EEPROM, RJ-45 female jack, etc)
* Obtain footprints of all chips, connectors, jacks, etc
* PCB layout
* Prototype PCB
* Design bus board
* Design [[SiPM Amplifier|analog board]]

Programming the Ethernet controller

2007-07-19T15:41:00Z

Krueger: /* (111) Transmit "D" */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

=== (110) Program DAC ===

This block will have a substate to obtain the programming mask. It then loops 32 (or 24 or 16) times on a second substate that obtains the next programming value and, if the corresponding mask bit is high, programs that channel of the DAC. A mux may be needed to select the appropriate bit from the programming mask. It also updates the locally stored DAC channel values (which may be stored on the FPGA, the CP2200/1 Flash, or other) in preparation for a "D" response packet. Then it transitions to state 111.

=== (111) Transmit "D" ===

This block loads a "D" to the transmit buffer then loops 32 (or 24 or 16) times to load the locally stored DAC channel values to the transmit buffer. Once the full packet has been loaded, it sends the packet, then transitions to state 010.

Programming the Ethernet controller

2007-07-19T15:40:39Z

Krueger: /* (110) Program DAC */

Programming the Ethernet controller

2007-07-19T15:39:20Z

Krueger: /* (101) Transmit "S" */

Programming the Ethernet controller

2007-07-19T15:38:55Z

Krueger: /* (011) Read Packet */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. A query has no switches or masks on it, so a "Q" packet will be discarded from the CP2200/1 before continuing on. A "P" packet has a large amount of data attached to it, so that is the only packet not discarded before continuing to the next state. This allows later states to access the packet data, but also puts on those later states the responsibility for discarding the packet once finished with it.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, it discards the received packet and transitions to state 010. ''Note: Received packet can be discarded anywhere in state 100 or 101. The discard functionality may even be relocated to the end of state 011, as that state already interacts with the CP2200/1.''

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Ethernet packets

2007-07-19T15:36:41Z

Krueger: /* "R" packet: reset */

'''This page deals with material under development. Please be aware that the information here may change as development proceeds.'''

This page details the packets we will send across our internal Ethernet to define the standards of communication between the digital boards and the controlling PC. Both the FPGA designer and the PC software programmer will need to make reference to this page in order to coordinate their respective designs.

== Open questions ==

* How will the FPGA obtain the MAC address of the PC? Can the cards broadcast, but filter out all packets not directly addressed to them? How would PC get board MAC addresses then? Print on PCB?

== Structure of a packet ==

[[Image:Ethernet packet.PNG|thumb|150px|right|A typical Ethernet packet.]]

=== Transmitting ===

To the right is a diagram depicting the structure of an Ethernet packet. On the left side is marked the blocks that must be defined by the FPGA to be passed to the CP2200/1. The first 8 bytes ("Preamble and Start Frame Delimiter") and last 4 bytes ("CRC") will be generated by the CP2200/1, so the FPGA need not even be aware of them. The first significant block is the 6-byte destination MAC address. The FPGA will have to store this (internally or using the RAM supplied by the CP2200/1) and then insert it into the appropriate place. The next block is the 6-byte source MAC address. Each CP2200/1 comes with a factory-set unique MAC address stored in the last page of Flash memory that will be used as the source MAC address. The next block is the 2-byte length block. This is the number of bytes of data, which can be as small as 46 or as large as 1,500. Then finally comes the data block, which must be padded to a minimum of 46 bytes but can not exceed 1,500 bytes.

=== Receiving ===

The CP2200/1 appears to give access to the entire 64-byte (minimum) packet, which would include everything on the above diagram except for the "Preamble and Start Frame Delimiter". The CP2200/2 can be programmed to filter out any packets not addressed to it. However, it only verifies the first 5 bytes of the MAC address. Checking the 6th byte and using the skip procedure is left to the FPGA. For good packets the FPGA can strip away and ignore the first 14 bytes (it does not need the length field, as we define our own standard for the packets below, using the first data byte to specify the type of packet). From there the FPGA can parse the data field according to the below specifications.

== Our packets ==

We will use six types of packets in our communications, paired into three "conversations" or "cycles": a reset cycle, a query cycle, a programming cycle. Each packet's data section will begin with a single-byte code to identify the packet type. As a mnemonic, these bytes will use ASCII codes to represent a single-letter shorthand for each packet.

=== The reset cycle ===

The reset cycle is a conversation whose purpose is to reset the digital control board. On each power-on, the various chips on the digital board need to be re-initialized. This includes the Ethernet chip itself, so the reset functionality needs to be built into the FPGA logic by default and needs to execute on start-up with no external stimulus in order to obtain Ethernet control. However it may also be necessary to instigate a reset externally for some reason. This cycle allows the external PC to initiate a reset and will notify the PC when the system is fully initialized.

==== "R" packet: reset ====

This is the packet sent from the PC to the card to initiate a reset process. Two possible reset packet ideas can be considered:
* Full reset: This resets all chips on the board (except for the FPGA; that should reset only during a power-up) together. This will contain no data.
* Selective reset: This will have flags to reset the Ethernet chip, the ADC, the temperature sensor, and the DAC. Combinations of flags allow a selective reset of any combination of the four chips. This will contain four flags which can be packaged into a single byte.
The first data byte will be an ASCII '''R''': 0x52, 0101 0010. For a full-reset-only design, all remaining bytes in the packet will be padding that the FPGA can ignore. For a selective-reset design, the second data byte will contain the four flags, and all bytes after that will be padding. A selective-reset design allows a form of "Are you awake" query to the board: Send a reset packet with all reset flags turned off; the system will not reset any devices but will still respond with an "I" packet. This may be an unnecessary feature, as the query cycle already acts as a more complex "Are you awake" query.

==== "I" packet: initialization complete ====

This is the acknowledgment packet sent from the FPGA to the PC to state that the reset cycle has been completed and the digital board is ready to resume regular operations. At this point all settings on the digital board have returned to their defaults (likely to mean all DAC channels set to zero). There is no data associated with this packet, so the only significant byte is the first byte, an ASCII '''I''': 0x49, 0100 1001.

=== The query cycle ===

The query cycle is a conversation regarding the status of the digital board. It polls the sensor devices and reports back their most recent data.

==== "Q" packet: query ====

This is the packet sent from the PC to the FPGA to request a status report. This could be made selective (status of ADC only, status of temperature sensor only, or full status report). However, as the size of an Ethernet packet is so large compared to the amount of data being requested, all data will be sent and the PC can use the data as it desires. Thus there is no data attached to a query packet. The first byte is an ASCII '''Q''': 0x51, 0101 0001.

==== "S" packet: status report ====

This is the packet sent from the FPGA to the PC to report on the current status of the board. The first byte of the packet will be an ASCII '''S''': 0x53, 0101 0011. After that will come the status data.
* The first two bytes of data will be the temperature. The temperature sensor returns 10 bits of data. The first byte will contain six leading zeros, then the two MSB of data. The second byte will contain the 8 LSB of data. An alternate scheme would be to convert the 10-bit two's-complement data into 16-bit two's-complement data and return that in two bytes.
* The next 16 bytes of data will be the ADC channels. The ADC returns 8 channels of 12 bits each. The first byte for each channel will have four leading zeros, then the 4 MSB of the data. The second byte for each channel will contain the 8 LSB of the data. The channels will be reported from channel zero to channel seven. An alternate scheme would be to convert the 12-bit two's-complement data into 16-bit two's-complement data and return that in two bytes each.
This totals 19 bytes: one of ASCII, two of temperature, sixteen of voltages.

=== The programming cycle ===

The programming cycle is a conversation intended to set the values of the DAC channels. It sends programming data to the board and receives confirmation of the programming.

==== "P" packet: programming ====

This is the packet sent from the PC to the FPGA to set new values to the DAC channels. The first byte of the packet will be an ASCII '''P''': 0x50, 0101 0000. The next four bytes (if all 32 channels are used; 3 if 24 channels, 2 bytes if 16 channels) together form a programming mask. Any channel that is to be reprogrammed will have a 1 in the corresponding location, and any channel that is to be left alone will have a 0 in the corresponding location. The MSB of the first byte will be channel 31 (or 23 or 15) and the LSB of the fourth (or third or second) byte will be channel 0. Thus, if all 32 channels are to be used, but only channels 14 through 26 are to be programmed, the packet would contain:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
! First data byte
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1
|-
! Second data byte
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1
|-
! Third data byte
| 1 || 1 || 0 || 0 || 0 || 0 || 0 || 0
|-
! Fourth data byte
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0
|}
Following this are 64 (or 48 or 32) bytes of programming data. The first two bytes are for channel 31 (or 23 or 15) and the last two bytes are for channel 0. Each channel has 14 bits, so the format is two leading zeros and 6 MSB of data is the first byte, then 8 LSB of data in the second byte. All channels are present in the packet, but only those marked in the mask will be programmed; all other bytes will be ignored and can take on any value. The total size of the data in a programming packet is:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! Number of channels
|
! Data Bytes per Packet
|-
| 32 || || 69
|-
| 24 || || 52
|-
| 16 || || 35*
|}
Since the minimum number of data bytes in a packet is 46, the packet may need to be padded if only 16 channels are to be used. Alternately the mask can be eliminated, forcing all channels of the DAC to be reprogrammed every programming cycle; however, having a mask allows a query of all DAC channels: set the mask to all zeros to reprogram nothing and the response will report back channel values according to the FPGA.

==== "D" packet: DAC setup complete ====

This is the packet sent from the FPGA to the PC to confirm that the DAC has been programmed to specifications. The first byte of this packet is an ASCII '''D''': 0x44, 0100 0100. The next 64 (or 48 or 32) bytes are the values of each DAC channel. As before, the format is two leading zeros and 6 MSB of data in the first byte and 8 LSB of data in the second byte, channel 31 (or 23 or 15) first, channel 0 last. This confirms to the PC that the data was programmed according to specification and helps synchronize the control board and the PC. All channels are reported back, not just those that were reprogrammed during this conversation. This will require that the FPGA (or the RAM in the Ethernet chip) store the values of the DAC channels, as the DAC has no interface to report back the value of a given channel. The size of this packet will be 4 (or 3 or 2) bytes less than for the corresponding programming packet, to account for the programming mask.

Programming the Ethernet controller

2007-07-19T15:35:07Z

Krueger: /* (101) Transmit "S" */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. "Q" and "P" packets simply transition to the next state, allowing the following states to access the rest of the packet.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.

=== (101) Transmit "S" ===

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, it discards the received packet and transitions to state 010. ''Note: Received packet can be discarded anywhere in state 100 or 101. The discard functionality may even be relocated to the end of state 011, as that state already interacts with the CP2200/1.''

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:33:41Z

Krueger: /* (100) Poll Status */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. "Q" and "P" packets simply transition to the next state, allowing the following states to access the rest of the packet.

=== (100) Poll Status ===

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Once all status values have been updated it transitions to state 101.

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:33:14Z

Krueger: /* (011) Read Packet */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

Block 011 is the first block with switching between following states. Its first task is to load the MAC data of the packet. If filtering inside of the FPGA is required, this block is responsible for it. The only MAC filtering likely to be needed is a check to see if the destination MAC address matches the MAC address of the CP2200/1, but the CP2200/1 should filter this itself (verify in the data sheet). If the packet is bad, this block tells the CP2200/1 to skip the packet and returns to block 010. The MAC filter would be the first substate.

After MAC filtering comes the second substate (or the only substate if MAC filtering is found to be unnecessary). This reads the first byte of the packet's data and uses it as a switch to determine the transition to the next state:
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
! ASCII
|
! Next State
|-
| R || || 000
|-
| Q || || 100
|-
| P || || 110
|-
| other || || 010
|}
Anything other than the three defined packets is considered a bad packet and is discarded in the CP2200/1 before transitioning back to state 010. An "R" packet obtains the reset mask from the second byte then discards the packet before transitioning to state 000. State 000 assumes that the reset mask is held, so this output needs to be latched in place until the next time this block activates. "Q" and "P" packets simply transition to the next state, allowing the following states to access the rest of the packet.

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:30:38Z

Krueger: /* (010) Idle */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

Block 010 continuously polls the interrupt registers on the CP2200/1 until the Receive FIFO Empty flag comes back as a zero. On this condition it transitions to state 011.

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:29:52Z

Krueger: /* (001) Transmit "I" */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (zeros) in all remaining bits. The CP2200/1 may handle padding itself; this will have to be verified in the data sheet. After the transmission is complete, the block writes a 010 to the state register.

=== (010) Idle ===

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:28:24Z

Krueger: /* (000) Reset Cycle */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== The eight states ==

There are eight major states to the module.

=== State list ===

; (000) Reset Cycle
: The reset cycle resets the selected chips. There are flags for resetting all 4 chips: DAC, ADC, temperature sensor, Ethernet controller. This is the entry state from a power-on. From this state, proceed unconditionally to 001.
; (001) Transmit "I"
: This state transmits an "I" packet to acknowledge that a reset occurred but the board is now prepared to accept new packets and function normally. From this state, proceed unconditionally to 010.
; (010) Idle
: This is the idle state where the state machine awaits a new packet's arrival. If the Receive FIFO is empty, it loops back on itself and continues checking the FIFO. If the FIFO is not empty, proceed to 011.
; (011) Read Packet
: This state accesses the first packet. If packets need to be filtered by the FPGA, this state will filter and return to 010 on a bad packet. The MAC data is discarded, as it is unimportant to the FPGA, and the first data byte is read. This byte is used as a switch: an ASCII "R" loops to 000. A "Q" proceeds to 100. A "P" proceeds to 110. Any other value is a bad packet and the state machine returns to 010.
; (100) Poll Status
: This state polls the status chips (the ADC and the temperature sensor) so that recent data is ready for transmission.
; (101) Transmit "S"
: This state packages and transmits an "S" packet over the Ethernet to report back the status of the board in response to a "Q" packet.
; (110) Program DAC
: This state programs the DAC with new values according to the mask and data in the "P" packet.
; (111) Transmit "D"
: This state packages and transmits a "D" packet over the Ethernet to report back the DAC voltages in response to a "P" packet.

=== State interconnect ===

These states will form the outline of the functional block diagram. Within each state will be a smaller process or set of processes, possibly broken into substates. Additionally we will have a central ''state'' register. Each block reads the state value in the register and enables itself upon seeing its own value. After completion of its function, a block will write a new value to the state register to enable the next block.

=== State variable ===

Based on the assignments of state values to the various states, certain interpretations of the state's bits arise. They may or may not prove useful in coding the system. They are given here in the case that they do become useful.
* S2:1:
** S2 = 0: "Core cycle" that executes regularly and forms the spine of the state diagram.
*** S2:1 = 00: "Initialization cycle" that prepares the state diagram for normal functioning.
*** S2:1 = 01: "Standard cycle" that the state machine returns to most frequently to process appropriate switching to branches.
** S2 = 1: "Branch cycles" that execute selectively based on received packets.
*** S2:1 = 10: "Query cycle" as described in the page on [[Ethernet packets]].
*** S2:1 = 11: "Programming cycle" as described in the page on [[Ethernet packets]].
* S0:
** S0 = 0: "Setup state" to prepare internal workings for a communication.
** S0 = 1: "Transfer state" to communicate with the external PC.

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]].

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

=== (010) Idle ===

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:25:18Z

Krueger:

Programming the Ethernet controller

2007-07-19T15:22:21Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus
* '''state register'''
** A three-bit register to store the current state.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
*** ''En'': write enable
*** ''D'': three-bit data-in bus
** outputs
*** ''Q'': three-bit data-out bus

=== (000) Reset Cycle ===

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

=== (010) Idle ===

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:19:24Z

Krueger: /* (000) Reset Cycle */

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus

=== (000) Reset Cycle ===

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high

=== (001) Transmit "I" ===

=== (010) Idle ===

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T15:03:03Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus

=== (000) Reset Cycle ===

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state counter as an enable (thereby incrementing the ''State'' to 001)

=== (001) Transmit "I" ===

=== (010) Idle ===

inputs:
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''TxRx_A'': 8-bit address from transceiver
* ''TxRx_D'': 8-bit data from transceiver
* ''TxRx_Done'': pulse from transceiver to signal transfer complete

internal signals
* ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)''
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle

blocks
* '''Fetcher'''
** Reads register 0x76 (INT0RD) by sending a read request to the transceiver
** inputs
*** ''F_Go'': pulse to start request, ''F_Go'' <= ''Go'' or ''Loop''
** outputs
*** ''TxRx_Go'': ''Go'' line on transceiver
*** ''TxRx_R/W'': ''R/W'' line on transceiver, tied high (read)
*** ''TxRx_A'': ''A_in'' bus on transceiver, tied to 0x76 (0111 0110)
**** Note: ''D_in'' on transceiver is not used; assume this line defaults to zero
* '''Looper'''
** Switch to determine if this state should loop on itself or continue to the next state.
** inputs
*** ''S_En'': state enable
*** ''TxRx_Done'': ''Done'' pulse from transceiver
*** ''TxRx_Data'': ''D_out'' bus from transceiver
** outputs
*** ''Loop'': pulse to repeat fetch cycle; ''Loop'' <= ''S_En'' and ''TxRx_Done'' and ''TxRx_Data(6)''
*** ''Done'': pulse to finish state; connects to state counter as an enable in order to increment the state to 011; ''Done'' <= ''S_En'' and ''TxRx_Done'' and not ''TxRx_Data(6)''

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T14:41:03Z

Krueger:

== Interface ==

:''See also: [[Ethernet packets]]''
:''See also: [[Ethernet state diagram]]''

== Emulator ==

== Controller ==

* '''transceiver'''
** This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
** inputs
*** ''CLK'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin a transmission
*** ''R/W_in'': read/write toggle: active-high read, active-low write
*** ''A_in'': 8-bit bus for address to read to/write from
*** ''D_in'': 8-bit bus for data to write; ignored during a read
** outputs to internals
*** ''Done'': pulse to signal completion of a transmission
*** ''R/W_out'': read/write flag: active-high read, active-low write
*** ''A_out'': 8-bit bus for address of last read/write
*** ''D_out'': 8-bit bus for data of last read; internal systems should ignore for a write
** outputs to CP2200/1
*** ''/CS'': active-low chip select
*** ''MotEn'': Motorola/Intel format toggle: active-high Motorola, active-low Intel
*** ''MuxEn'': Multiplexed flag; not used for CP2201
*** ''ALE'': ALE strobe
*** ''/Wr'': Active-low write flag
*** ''/Rd'': Active-low read flag
** inouts
*** ''AD'': 8-bit address and data bus

=== (000) Reset Cycle ===

inputs
* ''Clk'': clock
* ''/Rst'': asynchronous, active-low reset
* ''State'': 3-bit state value
* ''D_En'': DAC enable, assume held high/low by previous block
* ''A_En'': ADC enable, assume held high/low by previous block
* ''E_En'': Ethernet enable, assume held high/low by previous block

internal signals
* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''

blocks
* '''DAC Reset'''
** Resets and initializes the DAC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_Go'': go pulse to begin reset/initialization process
** outputs
*** - All DAC reset/initialization control lines -
*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
* '''ADC Reset'''
** Resets and initializes the ADC.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''A_Go'': go pulse to begin reset/initialization process
** outputs
*** - All ADC reset/initialization control lines -
*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
* '''Ethernet Reset'''
** Resets and initializes the Ethernet controller.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''E_Go'': go pulse to begin reset/initialization process
** outputs
*** - All Ethernet reset/initialization control lines -
*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
* '''Coordinator'''
** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''D_En'': high when DAC is to be reset
*** ''D_Done'': high when DAC is done resetting
*** ''A_En'': high when ADC is to be reset
*** ''A_Done'': high when ADC is done resetting
*** ''E_En'': high when Ethernet controller is to be reset
*** ''E_Done'': high when Ethernet controller is done resetting
** internal signals
*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
** outputs
*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state counter as an enable (thereby incrementing the ''State'' to 001)

=== (001) Transmit "I" ===

=== (010) Idle ===

=== (011) Read Packet ===

=== (100) Poll Status ===

=== (101) Transmit "S" ===

=== (110) Program DAC ===

=== (111) Transmit "D" ===

Programming the Ethernet controller

2007-07-19T14:36:03Z

Krueger: /* (000) Reset Cycle */

Programming the Ethernet controller

2007-07-19T14:32:17Z

Krueger: /* (000) Reset Cycle */

Programming the Ethernet controller

2007-07-19T14:27:57Z

Krueger: