<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/TotalTest/FPGA_test_isim_beh.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="basiccomp" />
            <top_module name="fpga_config" />
            <top_module name="fpga_test" />
            <top_module name="maincomp" />
            <top_module name="numeric_std" />
            <top_module name="std_logic_1164" />
            <top_module name="std_logic_arith" />
            <top_module name="std_logic_signed" />
            <top_module name="std_logic_textio" />
            <top_module name="std_logic_unsigned" />
            <top_module name="textio" />
            <top_module name="vcomponents" />
            <top_module name="vital_primitives" />
            <top_module name="vital_timing" />
            <top_module name="vpkg" />
         </top_modules>
      </db_ref>
   </db_ref_list>
   <WVObjectSize size="31" />
   <wvobject fp_name="/fpga_test/clk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clk</obj_property>
      <obj_property name="ObjectShortName">clk</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/rst" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">rst</obj_property>
      <obj_property name="ObjectShortName">rst</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/extrst_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">extrst_low</obj_property>
      <obj_property name="ObjectShortName">extrst_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/state_qout" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">state_qout[2:0]</obj_property>
      <obj_property name="ObjectShortName">state_qout[2:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/FPGA_main_inst/SerialOutFIFO_inst/go" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">go</obj_property>
      <obj_property name="ObjectShortName">go</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/serial_port" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">serial_port</obj_property>
      <obj_property name="ObjectShortName">serial_port</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_clk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_clk</obj_property>
      <obj_property name="ObjectShortName">eth_clk</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_ale" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_ale</obj_property>
      <obj_property name="ObjectShortName">eth_ale</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_rd_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_rd_low</obj_property>
      <obj_property name="ObjectShortName">eth_rd_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_wr_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_wr_low</obj_property>
      <obj_property name="ObjectShortName">eth_wr_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_ad" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">eth_ad[7:0]</obj_property>
      <obj_property name="ObjectShortName">eth_ad[7:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_cs_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_cs_low</obj_property>
      <obj_property name="ObjectShortName">eth_cs_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/int_request" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">int_request</obj_property>
      <obj_property name="ObjectShortName">int_request</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/int_type" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">int_type[15:0]</obj_property>
      <obj_property name="ObjectShortName">int_type[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_int_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_int_low</obj_property>
      <obj_property name="ObjectShortName">eth_int_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_rst_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_rst_low</obj_property>
      <obj_property name="ObjectShortName">eth_rst_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/eth_rstx_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">eth_rstx_low</obj_property>
      <obj_property name="ObjectShortName">eth_rstx_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/locstamp" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">locstamp[4:0]</obj_property>
      <obj_property name="ObjectShortName">locstamp[4:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/go_getpacket" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">go_getpacket[2:0]</obj_property>
      <obj_property name="ObjectShortName">go_getpacket[2:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_sdo" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_sdo</obj_property>
      <obj_property name="ObjectShortName">spi_sdo</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_sclk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_sclk</obj_property>
      <obj_property name="ObjectShortName">spi_sclk</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_rst_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_rst_low</obj_property>
      <obj_property name="ObjectShortName">spi_rst_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_t_ce" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_t_ce</obj_property>
      <obj_property name="ObjectShortName">spi_t_ce</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_a_cs_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_a_cs_low</obj_property>
      <obj_property name="ObjectShortName">spi_a_cs_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_sdi_tri" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_sdi_tri</obj_property>
      <obj_property name="ObjectShortName">spi_sdi_tri</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_a_error" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_a_error</obj_property>
      <obj_property name="ObjectShortName">spi_a_error</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/spi_t_error" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">spi_t_error</obj_property>
      <obj_property name="ObjectShortName">spi_t_error</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/dac_sclk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">dac_sclk</obj_property>
      <obj_property name="ObjectShortName">dac_sclk</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/dac_reset_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">dac_reset_low</obj_property>
      <obj_property name="ObjectShortName">dac_reset_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/dac_sync_low" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">dac_sync_low</obj_property>
      <obj_property name="ObjectShortName">dac_sync_low</obj_property>
   </wvobject>
   <wvobject fp_name="/fpga_test/dac_din" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">dac_din</obj_property>
      <obj_property name="ObjectShortName">dac_din</obj_property>
   </wvobject>
</wave_config>
