<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <!--                                                          -->

  <!--             For tool use only. Do not edit.              -->

  <!--                                                          -->

  <!-- ProjectNavigator created generated project file.         -->

  <!-- For use in tracking generated file and other information -->

  <!-- allowing preservation of process status.                 -->

  <!--                                                          -->

  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->

  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>

  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="TotalTest.xise"/>

  <files xmlns="http://www.xilinx.com/XMLSchema">
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="ADC_emulator_isim_beh.exe"/>
    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DAC_register_stx_beh.prj"/>
    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FPGA_main_stx_beh.prj"/>
    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="FPGA_test.cmd_log"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="FPGA_test.lso"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="FPGA_test.ngc"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="FPGA_test.ngr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FPGA_test.prj"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="FPGA_test.stx"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="FPGA_test.syr"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="FPGA_test.xst"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FPGA_test_beh.prj"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="FPGA_test_envsettings.html"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="FPGA_test_isim_beh.exe"/>
    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="FPGA_test_isim_beh.wdb"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FPGA_test_stx_beh.prj"/>
    <file xil_pn:fileType="FILE_HTML" xil_pn:name="FPGA_test_summary.html"/>
    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FPGA_test_vhdl.prj"/>
    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="FPGA_test_xst.xrpt"/>
    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
    <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
    <transform xil_pn:end_ts="1388694959" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388694959" xil_pn:in_ck="-2996774299779341283" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="../DAC_v2/DAC_controller.vhd"/>
      <outfile xil_pn:name="../DAC_v2/DAC_writer.vhd"/>
      <outfile xil_pn:name="../Ethernet/INTCatcher/INTCatcher.vhd"/>
      <outfile xil_pn:name="../Ethernet/Receiver/ReadPpacket.vhd"/>
      <outfile xil_pn:name="../Ethernet/Receiver/Receiver.vhd"/>
      <outfile xil_pn:name="../Ethernet/Reset/MACaddrLoad.vhd"/>
      <outfile xil_pn:name="../Ethernet/Reset/ResetHard.vhd"/>
      <outfile xil_pn:name="../Ethernet/Reset/ResetSoft.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transceiver/Transceiver.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transmitter/Transmitter.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transmitter/WriteDpacket.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transmitter/WriteSpacket.vhd"/>
      <outfile xil_pn:name="../FPGA_config.vhd"/>
      <outfile xil_pn:name="../FPGA_main.vhd"/>
      <outfile xil_pn:name="../Includes.vhd"/>
      <outfile xil_pn:name="../SerialOut.vhd"/>
      <outfile xil_pn:name="../Status/GetADCval.vhd"/>
      <outfile xil_pn:name="../Status/GetTempVal.vhd"/>
      <outfile xil_pn:name="../Status/Querier.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_creg.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_demux.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_emulator.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_error.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_shift_in16.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_shift_out16.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_demux.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_emulator.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_follow.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_register.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_shifter.vhd"/>
      <outfile xil_pn:name="Eth_emulator/Eth_emulator.vhd"/>
      <outfile xil_pn:name="Eth_emulator/FileRead.vhd"/>
      <outfile xil_pn:name="Eth_emulator/FileWrite.vhd"/>
      <outfile xil_pn:name="Eth_emulator/Regs.vhd"/>
      <outfile xil_pn:name="Eth_emulator/RxRegs.vhd"/>
      <outfile xil_pn:name="FPGA_test.vhd"/>
      <outfile xil_pn:name="Temp_emulator/Temp_emulator.vhd"/>
      <outfile xil_pn:name="Temp_emulator/Temp_error.vhd"/>
      <outfile xil_pn:name="Temp_emulator/Temp_shift.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1388694959" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-7796059726354259072" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388694959" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-2277306158470637752" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388694959" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="5025271837466729734" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388694959" xil_pn:in_ck="-2996774299779341283" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="../DAC_v2/DAC_controller.vhd"/>
      <outfile xil_pn:name="../DAC_v2/DAC_writer.vhd"/>
      <outfile xil_pn:name="../Ethernet/INTCatcher/INTCatcher.vhd"/>
      <outfile xil_pn:name="../Ethernet/Receiver/ReadPpacket.vhd"/>
      <outfile xil_pn:name="../Ethernet/Receiver/Receiver.vhd"/>
      <outfile xil_pn:name="../Ethernet/Reset/MACaddrLoad.vhd"/>
      <outfile xil_pn:name="../Ethernet/Reset/ResetHard.vhd"/>
      <outfile xil_pn:name="../Ethernet/Reset/ResetSoft.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transceiver/Transceiver.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transmitter/Transmitter.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transmitter/WriteDpacket.vhd"/>
      <outfile xil_pn:name="../Ethernet/Transmitter/WriteSpacket.vhd"/>
      <outfile xil_pn:name="../FPGA_config.vhd"/>
      <outfile xil_pn:name="../FPGA_main.vhd"/>
      <outfile xil_pn:name="../Includes.vhd"/>
      <outfile xil_pn:name="../SerialOut.vhd"/>
      <outfile xil_pn:name="../Status/GetADCval.vhd"/>
      <outfile xil_pn:name="../Status/GetTempVal.vhd"/>
      <outfile xil_pn:name="../Status/Querier.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_creg.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_demux.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_emulator.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_error.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_shift_in16.vhd"/>
      <outfile xil_pn:name="ADC_emulator/ADC_shift_out16.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_demux.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_emulator.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_follow.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_register.vhd"/>
      <outfile xil_pn:name="DAC_emulator/DAC_shifter.vhd"/>
      <outfile xil_pn:name="Eth_emulator/Eth_emulator.vhd"/>
      <outfile xil_pn:name="Eth_emulator/FileRead.vhd"/>
      <outfile xil_pn:name="Eth_emulator/FileWrite.vhd"/>
      <outfile xil_pn:name="Eth_emulator/Regs.vhd"/>
      <outfile xil_pn:name="Eth_emulator/RxRegs.vhd"/>
      <outfile xil_pn:name="FPGA_test.vhd"/>
      <outfile xil_pn:name="Temp_emulator/Temp_emulator.vhd"/>
      <outfile xil_pn:name="Temp_emulator/Temp_error.vhd"/>
      <outfile xil_pn:name="Temp_emulator/Temp_shift.vhd"/>
    </transform>
    <transform xil_pn:end_ts="1388694965" xil_pn:in_ck="-2996774299779341283" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1617745240074614351" xil_pn:start_ts="1388694959">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="FPGA_test_beh.prj"/>
      <outfile xil_pn:name="FPGA_test_isim_beh.exe"/>
      <outfile xil_pn:name="fuse.log"/>
      <outfile xil_pn:name="isim"/>
      <outfile xil_pn:name="isim.log"/>
      <outfile xil_pn:name="xilinxsim.ini"/>
    </transform>
    <transform xil_pn:end_ts="1388694965" xil_pn:in_ck="6290738825471218699" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1070069158840546018" xil_pn:start_ts="1388694965">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="OutputChanged"/>
      <outfile xil_pn:name="FPGA_test_isim_beh.wdb"/>
      <outfile xil_pn:name="isim.cmd"/>
      <outfile xil_pn:name="isim.log"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2963512372382260648" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5025271837466729734" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-7796059726354259072" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1430049303118697548" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388092153" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4924838950726155376" xil_pn:start_ts="1388092153">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1388613381" xil_pn:in_ck="5510954079952840682" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="3836079580555690669" xil_pn:start_ts="1388613377">
      <status xil_pn:value="FailedRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputAdded"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
    <transform xil_pn:end_ts="1388092161" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5064758191612568501" xil_pn:start_ts="1388092161">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
  </transforms>

</generated_project>
