Register <TxRx_Rd_reg> in unit <ResetSoft> has a constant value of 0 during circuit operation. The register is replaced by logic. Register <RAM_WE_reg> in unit <Transmitter> has a constant value of 00 during circuit operation. The register is replaced by logic. Register <RAM_DI_reg> in unit <Transmitter> has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. Register <TxRx_Rd_reg> in unit <Transmitter> has a constant value of 0 during circuit operation. The register is replaced by logic. Register <RAM_WE_reg> in unit <WriteDpacket> has a constant value of 00 during circuit operation. The register is replaced by logic. Register <RAM_DI_reg> in unit <WriteDpacket> has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. Register <TxRx_Rd_reg> in unit <WriteDpacket> has a constant value of 0 during circuit operation. The register is replaced by logic. Register <RAM_WE_reg> in unit <WriteSpacket> has a constant value of 00 during circuit operation. The register is replaced by logic. Register <TxRx_Rd_reg> in unit <WriteSpacket> has a constant value of 0 during circuit operation. The register is replaced by logic. "C:/Users/Richard Jones/Documents/GlueX/Tagger/Electronics/FPGA/Status/GetADCval.vhd" line 63: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <SCLK> Register <TxRx_D_reg> in unit <ReadPpacket> has a constant value of 00000000 during circuit operation. The register is replaced by logic. Register <RAM_WE_reg> in unit <DAC_writer> has a constant value of 00 during circuit operation. The register is replaced by logic. Register <RAM_DI_reg> in unit <DAC_writer> has a constant value of 0000000000000000 during circuit operation. The register is replaced by logic. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <RAM_DO> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <result<15>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <result<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <result<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Input <RAM_DO> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<15:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <MACcfg<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <MACcfg<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Input <INT_Found> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <RAM_DO> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <ADC_DIN_tri> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <packet_len<0><1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <packet_len<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <RAM_WEB> is used but never assigned. This sourceless signal will be automatically connected to value 00. Signal <RAM_SSRB> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <RAM_ENB> is used but never assigned. This sourceless signal will be automatically connected to value 1. Signal <RAM_DOPB> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <RAM_DOP> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <RAM_DOB> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <RAM_DIPB> is used but never assigned. This sourceless signal will be automatically connected to value 00. Signal <RAM_DIB> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000. Signal <RAM_ADDRB> is used but never assigned. This sourceless signal will be automatically connected to value 0000110110. HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. The FF/Latch <TxRx_A_reg_5> in Unit <MACaddrLoad_inst> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_6> The FF/Latch <RAM_ADDR_reg_3> in Unit <MACaddrLoad_inst> is equivalent to the following 7 FFs/Latches, which will be removed : <RAM_ADDR_reg_5> <RAM_ADDR_reg_6> <RAM_ADDR_reg_7> <RAM_ADDR_reg_8> <RAM_ADDR_reg_9> <TxRx_A_reg_4> <TxRx_A_reg_7> The FF/Latch <INT_Mask_reg_1> in Unit <ResetHard_inst> is equivalent to the following 4 FFs/Latches, which will be removed : <INT_Mask_reg_3> <INT_Mask_reg_8> <INT_Mask_reg_9> <INT_Mask_reg_10> The FF/Latch <TxRx_D_reg_7> in Unit <ResetSoft_inst> is equivalent to the following 6 FFs/Latches, which will be removed : <TxRx_A_reg_1> <TxRx_A_reg_2> <TxRx_A_reg_3> <TxRx_A_reg_5> <TxRx_A_reg_6> <TxRx_A_reg_7> The FF/Latch <TxRx_D_reg_1> in Unit <ResetSoft_inst> is equivalent to the following 2 FFs/Latches, which will be removed : <TxRx_A_reg_0> <TxRx_A_reg_4> The FF/Latch <INT_Mask_reg_15> in Unit <Transmitter_inst> is equivalent to the following 2 FFs/Latches, which will be removed : <TxRx_A_reg_5> <TxRx_A_reg_7> The FF/Latch <RAM_DI_reg_0> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_8> The FF/Latch <RAM_DI_reg_1> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_9> The FF/Latch <RAM_DI_reg_2> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_10> The FF/Latch <RAM_DI_reg_3> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_11> The FF/Latch <RAM_DI_reg_4> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_12> The FF/Latch <RAM_DI_reg_5> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_13> The FF/Latch <RAM_DI_reg_6> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_14> The FF/Latch <RAM_DI_reg_7> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_15> The FF/Latch <RAM_ADDR_reg_5> in Unit <PpacketReader> is equivalent to the following 3 FFs/Latches, which will be removed : <RAM_ADDR_reg_7> <RAM_ADDR_reg_8> <RAM_ADDR_reg_9> The FF/Latch <TxRx_Rd_reg> in Unit <PpacketReader> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_0> The FF/Latch <RAM_DI_reg_0> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_8> The FF/Latch <RAM_DI_reg_1> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_9> The FF/Latch <RAM_DI_reg_2> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_10> The FF/Latch <RAM_DI_reg_3> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_11> The FF/Latch <RAM_DI_reg_4> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_12> The FF/Latch <RAM_DI_reg_5> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_13> The FF/Latch <RAM_DI_reg_6> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_14> The FF/Latch <RAM_DI_reg_7> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_15> The FF/Latch <TxRx_D_reg_7> in Unit <Receiver_inst> is equivalent to the following 6 FFs/Latches, which will be removed : <TxRx_A_reg_1> <TxRx_A_reg_2> <TxRx_A_reg_3> <TxRx_A_reg_5> <TxRx_A_reg_6> <TxRx_A_reg_7> The FF/Latch <TxRx_D_reg_1> in Unit <Receiver_inst> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_4> The value init of the FF/Latch RAM_ADDR_reg_6 hinder the constant cleaning in the block PpacketReader. You should achieve better results by setting this init to 1. FF/Latch <TxRx_A_reg_4> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_3> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_2> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_1> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_DI_reg_15> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_DI_reg_14> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_DI_reg_13> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_DI_reg_12> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <Querier_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_15> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_14> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_13> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_12> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_11> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_10> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_9> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_8> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_7> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <PktType_Xmit_7> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <PktType_Xmit_5> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <PktType_Xmit_3> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <INTCatcher_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_7> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_6> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_5> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_4> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_3> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_2> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_0> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_3> has a constant value of 0 in block <Receiver_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_6> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_5> has a constant value of 0 in block <PpacketReader>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <WriteDpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <WriteDpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <WriteDpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_7> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_6> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_5> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_4> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_3> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_2> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_0> has a constant value of 0 in block <ResetSoft_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_15> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_14> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_13> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_12> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_11> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_7> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_6> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_4> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_2> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_0> has a constant value of 0 in block <ResetHard_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_3> has a constant value of 0 in block <MACaddrLoad_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_6> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_5> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_4> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_3> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_1> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_0> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_3> has a constant value of 0 in block <Transmitter_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <WriteSpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_5> has a constant value of 0 in block <WriteSpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <WriteSpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <WriteSpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <WriteSpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <WriteSpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <WriteDpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_5> has a constant value of 0 in block <WriteDpacket_inst>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <WriteDpacket_inst>. This FF/Latch will be trimmed during the optimization process. Node <MACcfg_0> of sequential type is unconnected in block <ResetHard_inst>. Node <MACcfg_1> of sequential type is unconnected in block <ResetHard_inst>. Node <MACcfg_2> of sequential type is unconnected in block <ResetHard_inst>. Node <MACcfg_3> of sequential type is unconnected in block <ResetHard_inst>. Node <MACcfg_5> of sequential type is unconnected in block <ResetHard_inst>. Node <MACcfg_6> of sequential type is unconnected in block <ResetHard_inst>. Node <MACcfg_7> of sequential type is unconnected in block <ResetHard_inst>. Node <packet_len_0_0> of sequential type is unconnected in block <Receiver_inst>. Node <packet_len_0_1> of sequential type is unconnected in block <Receiver_inst>. In order to maximize performance and save block RAM resources, the small ROM <Mrom_DAC_Code_reg_rom0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. In order to maximize performance and save block RAM resources, the small ROM <Mrom_DAC_Addr_reg_rom0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. In order to maximize performance and save block RAM resources, the small ROM <Mrom_DAC_margin_vec_rom0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. In order to maximize performance and save block RAM resources, the small ROM <Mrom_DAC_margin_vec_rom0001> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. In order to maximize performance and save block RAM resources, the small ROM <Mrom_DAC_value_vec_rom0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. In order to maximize performance and save block RAM resources, the small ROM <Mrom_more2do_var_mux0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. In order to maximize performance and save block RAM resources, the small ROM <Mrom_TxRx_A_reg_mux0002> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. Node <MACcfg_0> of sequential type is unconnected in block <ResetHard>. Node <MACcfg_1> of sequential type is unconnected in block <ResetHard>. Node <MACcfg_2> of sequential type is unconnected in block <ResetHard>. Node <MACcfg_3> of sequential type is unconnected in block <ResetHard>. Node <MACcfg_5> of sequential type is unconnected in block <ResetHard>. Node <MACcfg_6> of sequential type is unconnected in block <ResetHard>. Node <MACcfg_7> of sequential type is unconnected in block <ResetHard>. Node <packet_len_0_0> of sequential type is unconnected in block <Receiver>. Node <packet_len_0_1> of sequential type is unconnected in block <Receiver>. FF/Latch <RAM_ADDR_reg_3> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_4> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <MACaddrLoad>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <WriteDpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <WriteDpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <WriteDpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <WriteDpacket>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <WriteSpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <WriteSpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <WriteSpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <WriteSpacket>. This FF/Latch will be trimmed during the optimization process. The value init of the FF/Latch RAM_ADDR_reg_6 hinder the constant cleaning in the block ReadPpacket. You should achieve better results by setting this init to 1. FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_3> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_DI_reg_12> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_DI_reg_13> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_DI_reg_14> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_DI_reg_15> has a constant value of 0 in block <Querier>. This FF/Latch will be trimmed during the optimization process. FF/Latch <RAM_ADDR_reg_3> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_5> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_6> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_7> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_8> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <RAM_ADDR_reg_9> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. FF/Latch <PktType_Xmit_3> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <PktType_Xmit_5> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <PktType_Xmit_7> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. The FF/Latch <TxRx_A_reg_1> in Unit <ResetSoft> is equivalent to the following 6 FFs/Latches, which will be removed : <TxRx_A_reg_2> <TxRx_A_reg_3> <TxRx_A_reg_5> <TxRx_A_reg_6> <TxRx_A_reg_7> <TxRx_D_reg_7> The FF/Latch <TxRx_A_reg_0> in Unit <ResetSoft> is equivalent to the following 2 FFs/Latches, which will be removed : <TxRx_A_reg_4> <TxRx_D_reg_1> The FF/Latch <TxRx_A_reg_5> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_6> The FF/Latch <RAM_DI_reg_0> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_8> The FF/Latch <RAM_DI_reg_1> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_9> The FF/Latch <RAM_DI_reg_2> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_10> The FF/Latch <RAM_DI_reg_3> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_11> The FF/Latch <RAM_DI_reg_4> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_12> The FF/Latch <RAM_DI_reg_5> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_13> The FF/Latch <RAM_DI_reg_6> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_14> The FF/Latch <RAM_DI_reg_7> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_15> The FF/Latch <TxRx_Rd_reg> in Unit <ReadPpacket> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_0> The FF/Latch <INT_Mask_reg_1> in Unit <ResetHard> is equivalent to the following 4 FFs/Latches, which will be removed : <INT_Mask_reg_3> <INT_Mask_reg_8> <INT_Mask_reg_9> <INT_Mask_reg_10> The FF/Latch <INT_Mask_reg_15> in Unit <Transmitter> is equivalent to the following 2 FFs/Latches, which will be removed : <TxRx_A_reg_5> <TxRx_A_reg_7> The FF/Latch <RAM_DI_reg_0> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_8> The FF/Latch <RAM_DI_reg_1> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_9> The FF/Latch <RAM_DI_reg_2> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_10> The FF/Latch <RAM_DI_reg_3> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_11> The FF/Latch <RAM_DI_reg_4> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_12> The FF/Latch <RAM_DI_reg_5> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_13> The FF/Latch <RAM_DI_reg_6> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_14> The FF/Latch <RAM_DI_reg_7> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_15> The FF/Latch <TxRx_D_reg_7> in Unit <Receiver> is equivalent to the following 6 FFs/Latches, which will be removed : <TxRx_A_reg_1> <TxRx_A_reg_2> <TxRx_A_reg_3> <TxRx_A_reg_5> <TxRx_A_reg_6> <TxRx_A_reg_7> The FF/Latch <TxRx_D_reg_1> in Unit <Receiver> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_4> The FF/Latch <TxRx_A_reg_1> in Unit <ResetSoft> is equivalent to the following 6 FFs/Latches, which will be removed : <TxRx_D_reg_0> <TxRx_D_reg_2> <TxRx_D_reg_3> <TxRx_D_reg_4> <TxRx_D_reg_5> <TxRx_D_reg_6> FF/Latch <TxRx_A_reg_1> has a constant value of 0 in block <ResetSoft>. This FF/Latch will be trimmed during the optimization process. In block <DAC_writer>, ROM <Mrom_DAC_margin_vec_rom0001> FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <ResetHard>. This FF/Latch will be trimmed during the optimization process. Node <counter_8b_6> of sequential type is unconnected in block <ReadPpacket>. Node <counter_8b_7> of sequential type is unconnected in block <ReadPpacket>. Node <counter_32b_27> of sequential type is unconnected in block <ResetHard>. Node <counter_32b_28> of sequential type is unconnected in block <ResetHard>. Node <counter_32b_29> of sequential type is unconnected in block <ResetHard>. Node <counter_32b_30> of sequential type is unconnected in block <ResetHard>. Node <counter_32b_31> of sequential type is unconnected in block <ResetHard>. Instance RAMB16BWE_S18_S18_inst in unit FPGA_main of type RAMB16BWE_S18_S18 has been replaced by RAMB16BWE FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <INTCatcher>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_5> has a constant value of 0 in block <WriteDpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <WriteDpacket>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_5> has a constant value of 0 in block <WriteSpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <WriteSpacket>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_A_reg_1> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_2> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_3> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_4> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_5> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_6> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_A_reg_7> has a constant value of 0 in block <ReadPpacket>. This FF/Latch will be trimmed during the optimization process. FF/Latch <INT_Mask_reg_0> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_1> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_3> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_4> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_5> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_6> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_7> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_8> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_9> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_10> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_11> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_12> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_13> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_14> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <INT_Mask_reg_15> has a constant value of 0 in block <Transmitter>. This FF/Latch will be trimmed during the optimization process. FF/Latch <TxRx_D_reg_0> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_D_reg_2> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_D_reg_3> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_D_reg_4> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_D_reg_5> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_D_reg_6> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. Due to other FF/Latch trimming, FF/Latch <TxRx_D_reg_7> has a constant value of 0 in block <Receiver>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_15> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_14> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_13> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_12> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_11> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_7> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_6> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_4> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_2> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. FF/Latch <ResetHard_inst/INT_Mask_reg_0> has a constant value of 0 in block <FPGA_main>. This FF/Latch will be trimmed during the optimization process. The FF/Latch <TxRx_A_reg_5> in Unit <INTCatcher> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_6> The FF/Latch <TxRx_A_reg_3> in Unit <INTCatcher> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_4> The FF/Latch <RAM_DI_reg_5> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_13> The FF/Latch <RAM_DI_reg_4> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_12> The FF/Latch <RAM_DI_reg_7> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_15> The FF/Latch <RAM_DI_reg_3> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_11> The FF/Latch <RAM_DI_reg_6> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_14> The FF/Latch <RAM_DI_reg_2> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_10> The FF/Latch <RAM_DI_reg_1> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_9> The FF/Latch <RAM_DI_reg_0> in Unit <MACaddrLoad> is equivalent to the following FF/Latch, which will be removed : <RAM_DI_reg_8> The FF/Latch <TxRx_A_reg_4> in Unit <WriteDpacket> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_6> The FF/Latch <TxRx_A_reg_4> in Unit <WriteSpacket> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_6> The FF/Latch <TxRx_A_reg_4> in Unit <Transmitter> is equivalent to the following FF/Latch, which will be removed : <TxRx_A_reg_6> The FF/Latch <ResetHard_inst/TxRx_A_reg_6> in Unit <FPGA_main> is equivalent to the following FF/Latch, which will be removed : <ResetHard_inst/TxRx_A_reg_5> The FF/Latch <Transceiver_inst/stage_FSM_FFd7> in Unit <FPGA_main> is equivalent to the following FF/Latch, which will be removed : <Transceiver_inst/ALE_reg> Unit FPGA_main: 62 multi-source signals are replaced by logic (pull-up yes): Unit Receiver: 45 internal tristates are replaced by logic (pull-up yes): Unit Transmitter: 61 internal tristates are replaced by logic (pull-up yes): Unit MACaddrLoad: 45 internal tristates are replaced by logic (pull-up yes): Unit INTCatcher: 17 internal tristates are replaced by logic (pull-up yes): Unit DAC_writer: 28 internal tristates are replaced by logic (pull-up yes): Unit ResetSoft: 45 internal tristates are replaced by logic (pull-up yes): Unit ReadPpacket: 45 internal tristates are replaced by logic (pull-up yes): Unit WriteSpacket: 45 internal tristates are replaced by logic (pull-up yes): Unit WriteDpacket: 45 internal tristates are replaced by logic (pull-up yes): Node <INTCatcher_inst/Found_reg_15> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_13> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_12> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_14> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_11> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_9> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_7> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_6> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_8> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_5> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_4> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_3> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_1> of sequential type is unconnected in block <FPGA_main>. Node <INTCatcher_inst/Found_reg_2> of sequential type is unconnected in block <FPGA_main>. The FF/Latch <INTCatcher_inst/TxRx_D_reg_7> in Unit <FPGA_main> is equivalent to the following FF/Latch, which will be removed : <INTCatcher_inst/TxRx_D_reg_6>