Logical network STARTUP_SPARTAN3A_inst/GSR_INT has no load. Logical network STARTUP_SPARTAN3A_inst/GTS_INT has no load. No environment variables are currently set. All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_SPI_SCLK_OBUF/BUFG_inst_2" (output signal=SPI_SCLK_OBUF) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed): Pin CE of Querier_inst/GetTempVal_inst/counter_4b_0 Pin CE of Querier_inst/GetTempVal_inst/counter_4b_1 Pin CE of Querier_inst/GetTempVal_inst/counter_4b_2 Pin CE of Querier_inst/GetTempVal_inst/counter_4b_3 Pin CE of Querier_inst/GetTempVal_inst/Done_reg