Unit FPGA_BasicComp/Reg16x8bit_wPrim is now defined in a different file. It was defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd", and is now defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd". Unit FPGA_BasicComp/Reg16x8bit_wPrim/Behavioral is now defined in a different file. It was defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd", and is now defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd". Unit FPGA_BasicComp/Reg16x8bit_wPrim is now defined in a different file. It was defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd", and is now defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd". Unit FPGA_BasicComp/Reg16x8bit_wPrim/Behavioral is now defined in a different file. It was defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg256x8bit_wPrim.vhd", and is now defined in "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/Reg64x8bit_wPrim.vhd". "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 193: Unconnected output port 'db' of component 'INTCatcher'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 197: Unconnected output port 'TxRx_db' of component 'Transceiver'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 212: Unconnected output port 'db' of component 'SerialOutFIFO'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 235: Unconnected output port 'db' of component 'Transmitter'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 243: Unconnected output port 'db' of component 'Idler_ctrl'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 253: Unconnected output port 'db' of component 'Reader'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 257: Unconnected output port 'db1' of component 'Programmer_ctrl'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 257: Unconnected output port 'db2' of component 'Programmer_ctrl'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/MiscComp/EdgeCounter4bit.vhd" line 33: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <count1_sh> "E:/igors work/GlueX/Tagger/Electronics/FPGA/SerialOut.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <reg> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 130: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Done_Hash2> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 262: Unconnected output port 'db' of component 'MACwrToAddr'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 268: Unconnected output port 'db' of component 'MACwrToAddr'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 272: Unconnected output port 'db' of component 'MACwrToAddr'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 287: Unconnected output port 'db' of component 'MACwrToAddr'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 137: Unconnected output port 'db' of component 'MACwrToAddr'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 152: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Clk> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 168: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Clk> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/Transmitter_ctrl.vhd" line 268: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Rst>, <Go_TxStart> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/RAwr2BtoAddr.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <RamAddr>, <D>, <Data> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/S-Packet.vhd" line 96: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <TempReg_Q>, <ADCReg_Q> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 102: Unconnected output port 'ser_Go' of component 'GetTempVal'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 102: Unconnected output port 'ser_D' of component 'GetTempVal'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 102: Unconnected output port 'db' of component 'GetTempVal'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 139: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Rst> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetADCval.vhd" line 59: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <En>, <cnt>, <Addr_Q> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Rst> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 95: Unconnected output port 'Done' of component 'wrToAddr'. "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 105: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Clk> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 100: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <InitGo> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" line 110: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <InitGo> "E:/igors work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" line 187: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <InitGo>, <DataStage> Signal <db_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_AlmostDone> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <En_Convo> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 1-bit latch for signal <RWflag>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Found 1-bit latch for signal <Q>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Output <db> is never assigned. Tied to value 0. Signal <Go_late> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <AddrL> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <En_sh> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <En_sh> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <Mask> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <ser_LogStr> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_PhySta> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <INTval2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTval1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTname2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTname1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Go_INT2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_PhySTA> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <Done_INT0_delayed> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT1<7:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT1<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT0<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT0<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT0<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Output <DBbyte> is never assigned. Tied to value 00000000. Signal <Go_late> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <DBbyte_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <INT_Found<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <SPI_SDO2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <SPI_SDO1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Output <db> is never assigned. Tied to value 0. Input <DAC_Done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Output <db1> is never assigned. Tied to value 0. Output <db2> is never assigned. Tied to value 0. Signal <i> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <VoltDataMSB<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <PermitNextByte> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_CPLenH> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <Rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <RegSet> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <Rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <iClk> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Done_Byte_late> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <PktNum> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Output <db2> is never assigned. Tied to value 0. Signal <ser_Go_rc1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <WordCount> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go9> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go16> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <MACCfg<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <MACCfg<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Go_InitMAC> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_MACconfig> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_MACCF3> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_MACCF2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit latch for signal <db1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Input <INT_Done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Output <INT_Go> is never assigned. Tied to value 0. Signal <wrMACaddrs_db> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_uSpack> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_uCheck2> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <ser_Go_uCheck1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <ser_Go_ACL2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_ACL> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_uCheck2> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_uCheck1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_u0> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_ACL2> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_ACL> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <RAwrToAddr_db> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <RAwrGo_uTxLen> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <MACregs_A_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Len2B> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_TxStatCheck> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_TxBufCheck> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_Len> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <state_En_u1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_uResS> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_Quer> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <dbtmp1> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <db_serial_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbInfoCnt_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbInfoCnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbInfo> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_u1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_Idl> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Transmitter_db> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <StateChCnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <SPI_SDI_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Reset_hard_db2> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Reset_hard_db1> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Go_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <GTS_PORT> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <GSR_PORT> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <EthAccessCnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <DBbyte> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <DACtestAddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. Hierarchical block <uPktNum> is unconnected in block <uXmit>. It will be removed from the design. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 1 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 0 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. Node <Data_1> of sequential type is unconnected in block <r1>. Node <Data_3> of sequential type is unconnected in block <r1>. Node <Data_6> of sequential type is unconnected in block <r1>. Node <Data_7> of sequential type is unconnected in block <r1>. Node <Data_2> of sequential type is unconnected in block <r2>. Node <Data_4> of sequential type is unconnected in block <r2>. Node <Data_5> of sequential type is unconnected in block <r2>. Node <Data_6> of sequential type is unconnected in block <r2>. Node <Data_7> of sequential type is unconnected in block <r2>. Node <Data_0> of sequential type is unconnected in block <m1a>. Node <Data_1> of sequential type is unconnected in block <m1a>. Node <Data_2> of sequential type is unconnected in block <m1a>. Node <Data_3> of sequential type is unconnected in block <m1a>. Node <Data_5> of sequential type is unconnected in block <m1a>. Node <Data_6> of sequential type is unconnected in block <m1a>. Node <Data_7> of sequential type is unconnected in block <m1a>. Node <Data_6> of sequential type is unconnected in block <r1>. Node <Data_7> of sequential type is unconnected in block <r1>. Node <uResH/db1> of sequential type is unconnected in block <FPGA_ctrl>. Unit FPGA_ctrl: 23 multi-source signals are replaced by logic (pull-up yes): Unit INTCatcher: 8 internal tristates are replaced by logic (pull-up yes): Unit Reset_soft: 23 internal tristates are replaced by logic (pull-up yes): Unit Transmitter: 11 internal tristates are replaced by logic (pull-up yes): Unit Transmitter: 3 multi-source signals are replaced by logic (pull-up yes): Unit MACaddrLoad: 12 internal tristates are replaced by logic (pull-up yes): Unit Programmer_ctrl: 8 internal tristates are replaced by logic (pull-up yes): Unit Reader: 11 internal tristates are replaced by logic (pull-up yes): Unit Querier: 6 internal tristates are replaced by logic (pull-up yes): Unit Querier: 8 multi-source signals are replaced by logic (pull-up yes): Unit Idler_ctrl: 11 internal tristates are replaced by logic (pull-up yes): Unit GetTempVal: 9 internal tristates are replaced by logic (pull-up yes): Unit WrMACaddrs: 13 internal tristates are replaced by logic (pull-up yes): Unit GetADCval: 8 internal tristates are replaced by logic (pull-up yes): Unit GetADCval: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): Unit getByte: 17 internal tristates are replaced by logic (pull-up yes): Unit DPacket: 21 internal tristates are replaced by logic (pull-up yes): Unit SPacket: 11 internal tristates are replaced by logic (pull-up yes): Unit RAwr2BtoAddr: 24 internal tristates are replaced by logic (pull-up yes): Unit wrToAddr: 17 internal tristates are replaced by logic (pull-up yes): FF/Latch <uXmit/RAwr_aH/AddrL_reg_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_0> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_4> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_1> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/AddrL_reg_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_6> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_4> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_3> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxSt1/Data_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_0> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_1> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_2> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_4> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_1> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/AddrL_reg_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_6> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_4> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_3> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uTxS2/Data_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_6> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_4> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/RAwr_aH/AddrL_reg_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_4> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_5> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_4> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/AddrL_reg_0> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_6> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_4> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_2> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_1> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uResH/m6/a1/Data_0> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_4> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/Data_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_3> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_4> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uDpack/u2/AddrL_reg_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_2> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_3> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_4> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_5> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_6> (without init value) has a constant value of 1 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/Data_7> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_0> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. FF/Latch <uXmit/uSpack/uTxSt1/AddrL_reg_1> (without init value) has a constant value of 0 in block <FPGA_ctrl>. This FF/Latch will be trimmed during the optimization process. Node <uRd/d/En> of sequential type is unconnected in block <FPGA_ctrl>. Node <uRd/d/En_sh> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_15> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_14> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_13> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_12> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_11> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_10> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_9> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_8> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_7> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_6> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_5> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_4> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_3> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_2> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_1> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/count_0> of sequential type is unconnected in block <FPGA_ctrl>. Node <uXmit/uPktNum/Go_sh> of sequential type is unconnected in block <FPGA_ctrl>. Node <uProg/r1/Data_7> of sequential type is unconnected in block <FPGA_ctrl>. Node <uProg/r1/Data_6> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r1/Data_7> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r1/Data_6> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r1/Data_3> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r1/Data_1> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r2/Data_7> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r2/Data_6> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r2/Data_5> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r2/Data_4> of sequential type is unconnected in block <FPGA_ctrl>. Node <uINT/r2/Data_2> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_7> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_6> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_5> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_3> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_2> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_1> of sequential type is unconnected in block <FPGA_ctrl>. Node <uResH/m1a/Data_0> of sequential type is unconnected in block <FPGA_ctrl>. Area constraint could not be met for block <FPGA_ctrl>, final ratio is 108. (*) More than 100% of Device resources are used HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.