The MAP option "No logic replication" (-l) is being deprecated in the next major software release. There will be a smaller percentage of guiding when using SmartGuide with the some of the physical synthesis options. These options include: "Combinatorial Logic Optimization"(-logic_opt),"Global Optimization"(-global_opt), and "Register Duplication"(-register_duplication). The command line used to create the guide file is: -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf The command line used for this run is: -ise TotalTest.ise -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol std -t 1 -register_duplication off -cm speed -detail -ir all -ignore_keep_hierarchy -pr b -l -ntd -bp -smartguide FPGA_ctrl_guide.ncd -power off -o FPGA_ctrl_map.ncd FPGA_ctrl.ngd FPGA_ctrl.pcf If one or more of the above physical synthesis options is being used, SmartGuide will have a lower guide percentage, possibly longer runtimes and possibly worse timing scores. If the physical synthesis option is required to meet timing, it is suggested that SmartGuide is not used. If the physical synthesis option is not required, it is suggested to re-create the guide without the physical synthesis option and re-run SmartGuide Logical network STARTUP_SPARTAN3A_inst/GSR_INT has no load. Logical network STARTUP_SPARTAN3A_inst/GTS_INT has no load. Logical network r6/u1/r0/reg1bit_0/SPO has no load. Logical network r6/u1/r0/reg1bit_1/SPO has no load. Logical network r6/u1/r0/reg1bit_2/SPO has no load. Logical network r6/u1/r0/reg1bit_3/SPO has no load. Logical network r6/u1/r0/reg1bit_4/SPO has no load. Logical network r6/u1/r0/reg1bit_5/SPO has no load. Logical network r6/u1/r0/reg1bit_6/SPO has no load. Logical network r6/u1/r0/reg1bit_7/SPO has no load. Logical network r6/u1/r0/reg1bit_8/SPO has no load. Logical network r6/u1/r0/reg1bit_9/SPO has no load. Logical network r6/u1/r0/reg1bit_10/SPO has no load. Logical network r6/u1/r0/reg1bit_11/SPO has no load. Logical network r6/u1/r0/reg1bit_12/SPO has no load. Logical network r6/u1/r0/reg1bit_13/SPO has no load. Logical network r6/u1/r1/reg1bit_0/SPO has no load. Logical network r6/u1/r1/reg1bit_1/SPO has no load. Logical network r6/u1/r1/reg1bit_2/SPO has no load. Logical network r6/u1/r1/reg1bit_3/SPO has no load. Logical network r6/u1/r1/reg1bit_4/SPO has no load. Logical network r6/u1/r1/reg1bit_5/SPO has no load. Logical network r6/u1/r1/reg1bit_6/SPO has no load. Logical network r6/u1/r1/reg1bit_7/SPO has no load. Logical network r6/u1/r1/reg1bit_8/SPO has no load. Logical network r6/u1/r1/reg1bit_9/SPO has no load. Logical network r6/u1/r1/reg1bit_10/SPO has no load. Logical network r6/u1/r1/reg1bit_11/SPO has no load. Logical network r6/u1/r1/reg1bit_12/SPO has no load. Logical network r6/u1/r1/reg1bit_13/SPO has no load. Logical network db0/r1/r3/reg1bit_7/SPO has no load. Logical network db0/r1/r3/reg1bit_6/SPO has no load. Logical network db0/r1/r3/reg1bit_5/SPO has no load. Logical network db0/r1/r3/reg1bit_4/SPO has no load. Logical network db0/r1/r3/reg1bit_3/SPO has no load. Logical network db0/r1/r3/reg1bit_2/SPO has no load. Logical network db0/r1/r3/reg1bit_1/SPO has no load. Logical network db0/r1/r3/reg1bit_0/SPO has no load. Logical network db0/r1/r2/reg1bit_7/SPO has no load. Logical network db0/r1/r2/reg1bit_6/SPO has no load. Logical network db0/r1/r2/reg1bit_5/SPO has no load. Logical network db0/r1/r2/reg1bit_4/SPO has no load. Logical network db0/r1/r2/reg1bit_3/SPO has no load. Logical network db0/r1/r2/reg1bit_2/SPO has no load. Logical network db0/r1/r2/reg1bit_1/SPO has no load. Logical network db0/r1/r2/reg1bit_0/SPO has no load. Logical network db0/r1/r1/reg1bit_7/SPO has no load. Logical network db0/r1/r1/reg1bit_6/SPO has no load. Logical network db0/r1/r1/reg1bit_5/SPO has no load. Logical network db0/r1/r1/reg1bit_4/SPO has no load. Logical network db0/r1/r1/reg1bit_3/SPO has no load. Logical network db0/r1/r1/reg1bit_2/SPO has no load. Logical network db0/r1/r1/reg1bit_1/SPO has no load. Logical network db0/r1/r1/reg1bit_0/SPO has no load. Logical network db0/r1/r0/reg1bit_7/SPO has no load. Logical network db0/r1/r0/reg1bit_6/SPO has no load. Logical network db0/r1/r0/reg1bit_5/SPO has no load. Logical network db0/r1/r0/reg1bit_4/SPO has no load. Logical network db0/r1/r0/reg1bit_3/SPO has no load. Logical network db0/r1/r0/reg1bit_2/SPO has no load. Logical network db0/r1/r0/reg1bit_1/SPO has no load. Logical network db0/r1/r0/reg1bit_0/SPO has no load. No environment variables are currently set. The following NGM file is used during SmartGuide: "FPGA_ctrl_map.ngm". The NGM file contains information on how the guide file was originally mapped. It is required for the best SmartGuide results. All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. The function generator TxRx_D<7>LogicTrst62_SW0_SW0 failed to merge with F5 multiplexer TxRx_A<7>LogicTrst1_SW4. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <fClk_out_OBUF_BUFG> is placed at site <BUFGMUX_X1Y1>. The IO component <fClk> is placed at site <PAD108>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <fClk.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair. The clock component <u1/DCM_SP_inst> is placed at site <DCM_X0Y0>. The clock IO/DCM site can be paired if they are placed/locked in the same quadrant. The IO component <fClk> is placed at site <PAD108>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <fClk.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. No timing constraints found, doing default enumeration. Map created a placed design. Gated clock. Clock net Rst_int is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net uXmit/uDpack/w/C_0_0_not0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net ser_Go_uINT is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net uResS/Done_Byte is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net uXmit/uSpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net uXmit/uDpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.