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    <!-- ISE source project file created by Project Navigator.             -->
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    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
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    <!-- implement in ISE Project Navigator.                               -->
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    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="-l" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Package" xil_pn:value="vq100" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|AwaitClearLink|Behavioral" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="Architecture|Eth_emulator_MuxIntelTest_vhd|behavior" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut1" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="0 ns" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Search Directories for 'Include" xil_pn:value="../../FPGA" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target UCF File Name" xil_pn:value="FPGA_ctrl.ucf" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="No" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="iMPACT Project File" xil_pn:value="fpga.ipf" xil_pn:valueState="non-default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SPI_test|behavior" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="TotalTest" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Architecture|Eth_emulator_MuxIntelTest_vhd|behavior" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|Eth_emulator_MuxIntelTest_vhd|behavior" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="Architecture|Eth_emulator_MuxIntelTest_vhd|behavior" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|Eth_emulator_MuxIntelTest_vhd|behavior" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

  <bindings>
    <binding xil_pn:location="/FPGA_ctrl" xil_pn:name="FPGA_ctrl.ucf"/>
  </bindings>

  <libraries>
    <library xil_pn:name="FPGA_BasicComp"/>
  </libraries>

  <partitions/>

</project>
