-- SerialOutFIFO_test Template 

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity SerialOutFIFO_test is
end SerialOutFIFO_test;

architecture behavior of SerialOutFIFO_test is 

	-- Component Declaration
 	component SerialOutFIFO is
	    port ( Clk : in  STD_LOGIC;
       		   Rst : in  STD_LOGIC;
		   Go : in STD_LOGIC;
		   D : in  STD_LOGIC_VECTOR (7 downto 0);
		   Q : out  STD_LOGIC
		 );
	end component;

	signal Clk :  std_logic;
	signal Rst :  std_logic := '1';
	signal ser_Go :  std_logic;
	signal db_serial : std_logic;
	signal ser_D :  std_logic_vector(7 downto 0);
          
	constant clk_period : time := 200ns;

begin

	-- Component Instantiation
	uut: SerialOutFIFO port map (
		Clk => Clk,
		Rst => Rst,
		Go => ser_Go,
		D => ser_D,
		Q => db_serial
		);

	genclk: process
	begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
	end process;


	--  Test Bench Statements
	tb : process
	begin
		wait for 100 ns; -- wait until global set/reset completes
		Rst <= '0'; ser_Go <= '0';
		wait for clk_period*2;
		
		------------------------------------------------------
		
		ser_Go <= '1'; ser_D <= X"30";
		wait for clk_period;
		ser_Go <= '0'; ser_D <= "ZZZZZZZZ";

		wait for 300000 ns; --------------------------

		ser_Go <= '1'; ser_D <= X"F7";
		wait for clk_period;
		ser_Go <= '0'; ser_D <= "ZZZZZZZZ";

		wait for clk_period; -------------------------

		ser_Go <= '1'; ser_D <= X"63";
		wait for clk_period;
		ser_Go <= '0'; ser_D <= "ZZZZZZZZ";

	------------------------------------------------------
		wait; -- will wait forever
	end process tb;
	--  End Test Bench 
end;