----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger, Igor Senderovich
-- 
-- Create Date:    16:28:37 07/17/2007 
-- Design Name: Delayer for SPI Controller
-- Module Name:    delay - delay_behavioral 
-- Project Name: SPI Module
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Delays a signal by one clock cycle
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity c_delay is
    Port ( Clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC
	 );
end c_delay;

architecture delay_behavioral of c_delay is

	signal Q_int : STD_LOGIC;

begin

	delayer : process (Clk)
	begin
		if falling_edge(Clk) then
			Q_int <= D;
		else
			Q_int <= Q_int;
		end if;
		
		if rising_edge(Clk) then
			Q <= Q_int;
		end if;
	
	end process delayer;

end delay_behavioral;

------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity c_dbldelay is
    Port ( Clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC
	 );
end c_dbldelay;

architecture dbldelay_behavioral of c_dbldelay is

	component c_delay is
    Port ( Clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
	end component;

	signal Q_interm : STD_LOGIC;

begin

	u1: c_delay port map (Clk, D, Q_interm);
	u2: c_delay port map (Clk, Q_interm, Q);

end dbldelay_behavioral;