----------------------------------------------------------------------------------
-- Company:   University of Connecticut
-- Engineer:  Igor Senderovich
-- 
-- Create Date:    09:40:38 11/12/2007 
-- Design Name: 
-- Module Name:    StepCounter16bit - Behavioral 
-- Description:    8-bit counter with triggered at every step
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity StepCounter16bit is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
	   Q   : out STD_LOGIC_VECTOR (15 downto 0)
	 );
end StepCounter16bit;

architecture Behavioral of StepCounter16bit is

	signal count : STD_LOGIC_VECTOR (15 downto 0);
	signal Go_sh : STD_LOGIC;

begin
		
	StepCounter16bit : process (Clk, Go, Rst)
	begin
		if (Rst='1') then
			count <= X"0000";
		else
			if falling_edge(Clk) then
				Go_sh <= Go;
			end if;

			if rising_edge(Clk) then
				count <= count + (X"000" & "000" & Go_sh);
			else
				count <= count;
			end if;
		end if;
	end process;
	
	Q <= count;

end Behavioral;