---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 10:22:64 09/24/2007 -- Design Name: Multiplexed Registers for DAC voltage values -- Module Name: Reg32x14bit_wPrim - Behavioral -- Description: 32 x 8bit muxed register bank using Xilinx primitives -- to avoid use of regular logic slices. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library UNISIM; --use UNISIM.VComponents.all; entity Reg32x14bit_wPrim is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Wr : in STD_LOGIC; Addri : in STD_LOGIC_VECTOR (4 downto 0); Addro : in STD_LOGIC_VECTOR (4 downto 0); D : in STD_LOGIC_VECTOR (13 downto 0); Q : out STD_LOGIC_VECTOR (13 downto 0) ); end Reg32x14bit_wPrim; architecture Behavioral of Reg32x14bit_wPrim is component Reg16x14bit_wPrim is Port ( Clk : in STD_LOGIC; En : in STD_LOGIC; Addri : in STD_LOGIC_VECTOR (3 downto 0); Addro : in STD_LOGIC_VECTOR (3 downto 0); D : in STD_LOGIC_VECTOR (13 downto 0); Q : out STD_LOGIC_VECTOR (13 downto 0) ); end component; signal Q0, Q1 : STD_LOGIC_VECTOR (13 downto 0); signal En_r0, En_r1, RegSet : STD_LOGIC; begin En_r0 <= Wr and not Addri(4); En_r1 <= Wr and Addri(4); r0: Reg16x14bit_wPrim port map (Clk, En_r0, Addri(3 downto 0), Addro(3 downto 0), D, Q0); r1: Reg16x14bit_wPrim port map (Clk, En_r1, Addri(3 downto 0), Addro(3 downto 0), D, Q1); Q <= Q0 when Addro(4)='0' else Q1 when Addro(4)='1'; end Behavioral; ---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 10:22:64 09/24/2007 -- Design Name: Multiplexed Registers for DAC voltage values -- Module Name: Reg16x8bit_wPrim - Behavioral -- Description: 16 x 8bit muxed register bank using Xilinx primitives -- to avoid use of regular logic slices. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity Reg16x14bit_wPrim is Port ( Clk : in STD_LOGIC; --Rst : in STD_LOGIC; En : in STD_LOGIC; Addri : in STD_LOGIC_VECTOR (3 downto 0); Addro : in STD_LOGIC_VECTOR (3 downto 0); D : in STD_LOGIC_VECTOR (13 downto 0); Q : out STD_LOGIC_VECTOR (13 downto 0) ); end Reg16x14bit_wPrim; architecture Behavioral of Reg16x14bit_wPrim is signal iClk : STD_LOGIC; begin iClk <= not Clk; reg1bit_0 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(0), D => D(0), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_1 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(1), D => D(1), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_2 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(2), D => D(2), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_3 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(3), D => D(3), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_4 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(4), D => D(4), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_5 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(5), D => D(5), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_6 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(6), D => D(6), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_7 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(7), D => D(7), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_8 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(8), D => D(8), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_9 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(9), D => D(9), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_10 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(10), D => D(10), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_11 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(11), D => D(11), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_12 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(12), D => D(12), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_13 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(13), D => D(13), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); end Behavioral;