---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 10:22:64 09/24/2007 -- Design Name: Multiplexed Registers for DAC voltage values -- Module Name: Reg256x8bit_wPrim - Behavioral -- Description: 256 x 8bit muxed register bank using Xilinx primitives -- to avoid use of regular logic slices. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --library UNISIM; --use UNISIM.VComponents.all; entity Reg256x8bit_wPrim is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Wr : in STD_LOGIC; Addri : in STD_LOGIC_VECTOR (7 downto 0); Addro : in STD_LOGIC_VECTOR (7 downto 0); D : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0) ); end Reg256x8bit_wPrim; architecture Behavioral of Reg256x8bit_wPrim is component Reg16x8bit_wPrim_2 is Port ( iClk : in STD_LOGIC; En : in STD_LOGIC; Addri : in STD_LOGIC_VECTOR (3 downto 0); Addro : in STD_LOGIC_VECTOR (3 downto 0); D : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0) ); end component; signal En : STD_LOGIC_VECTOR (15 downto 0); signal Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15 : STD_LOGIC_VECTOR (7 downto 0); signal iClk : STD_LOGIC; begin iClk <= not Clk; En(0) <= Wr when Addri(7 downto 4)=X"0" else '0'; En(1) <= Wr when Addri(7 downto 4)=X"1" else '0'; En(2) <= Wr when Addri(7 downto 4)=X"2" else '0'; En(3) <= Wr when Addri(7 downto 4)=X"3" else '0'; En(4) <= Wr when Addri(7 downto 4)=X"4" else '0'; En(5) <= Wr when Addri(7 downto 4)=X"5" else '0'; En(6) <= Wr when Addri(7 downto 4)=X"6" else '0'; En(7) <= Wr when Addri(7 downto 4)=X"7" else '0'; En(8) <= Wr when Addri(7 downto 4)=X"8" else '0'; En(9) <= Wr when Addri(7 downto 4)=X"9" else '0'; En(10) <= Wr when Addri(7 downto 4)=X"A" else '0'; En(11) <= Wr when Addri(7 downto 4)=X"B" else '0'; En(12) <= Wr when Addri(7 downto 4)=X"C" else '0'; En(13) <= Wr when Addri(7 downto 4)=X"D" else '0'; En(14) <= Wr when Addri(7 downto 4)=X"E" else '0'; En(15) <= Wr when Addri(7 downto 4)=X"F" else '0'; r0: Reg16x8bit_wPrim_2 port map (iClk, En(0), Addri(3 downto 0), Addro(3 downto 0), D, Q0); r1: Reg16x8bit_wPrim_2 port map (iClk, En(1), Addri(3 downto 0), Addro(3 downto 0), D, Q1); r2: Reg16x8bit_wPrim_2 port map (iClk, En(2), Addri(3 downto 0), Addro(3 downto 0), D, Q2); r3: Reg16x8bit_wPrim_2 port map (iClk, En(3), Addri(3 downto 0), Addro(3 downto 0), D, Q3); r4: Reg16x8bit_wPrim_2 port map (iClk, En(4), Addri(3 downto 0), Addro(3 downto 0), D, Q4); r5: Reg16x8bit_wPrim_2 port map (iClk, En(5), Addri(3 downto 0), Addro(3 downto 0), D, Q5); r6: Reg16x8bit_wPrim_2 port map (iClk, En(6), Addri(3 downto 0), Addro(3 downto 0), D, Q6); r7: Reg16x8bit_wPrim_2 port map (iClk, En(7), Addri(3 downto 0), Addro(3 downto 0), D, Q7); r8: Reg16x8bit_wPrim_2 port map (iClk, En(8), Addri(3 downto 0), Addro(3 downto 0), D, Q8); r9: Reg16x8bit_wPrim_2 port map (iClk, En(9), Addri(3 downto 0), Addro(3 downto 0), D, Q9); r10: Reg16x8bit_wPrim_2 port map (iClk, En(10), Addri(3 downto 0), Addro(3 downto 0), D, Q10); r11: Reg16x8bit_wPrim_2 port map (iClk, En(11), Addri(3 downto 0), Addro(3 downto 0), D, Q11); r12: Reg16x8bit_wPrim_2 port map (iClk, En(12), Addri(3 downto 0), Addro(3 downto 0), D, Q12); r13: Reg16x8bit_wPrim_2 port map (iClk, En(13), Addri(3 downto 0), Addro(3 downto 0), D, Q13); r14: Reg16x8bit_wPrim_2 port map (iClk, En(14), Addri(3 downto 0), Addro(3 downto 0), D, Q14); r15: Reg16x8bit_wPrim_2 port map (iClk, En(15), Addri(3 downto 0), Addro(3 downto 0), D, Q15); Q <= Q0 when Addro(7 downto 4)=X"0" else Q1 when Addro(7 downto 4)=X"1" else Q2 when Addro(7 downto 4)=X"2" else Q3 when Addro(7 downto 4)=X"3" else Q4 when Addro(7 downto 4)=X"4" else Q5 when Addro(7 downto 4)=X"5" else Q6 when Addro(7 downto 4)=X"6" else Q7 when Addro(7 downto 4)=X"7" else Q8 when Addro(7 downto 4)=X"8" else Q9 when Addro(7 downto 4)=X"9" else Q10 when Addro(7 downto 4)=X"A" else Q11 when Addro(7 downto 4)=X"B" else Q12 when Addro(7 downto 4)=X"C" else Q13 when Addro(7 downto 4)=X"D" else Q14 when Addro(7 downto 4)=X"E" else Q15 when Addro(7 downto 4)=X"F"; end Behavioral; ---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 10:22:64 09/24/2007 -- Design Name: Multiplexed Registers for DAC voltage values -- Module Name: Reg16x8bit_wPrim_2 - Behavioral -- Description: 16 x 8bit muxed register bank using Xilinx primitives -- to avoid use of regular logic slices. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity Reg16x8bit_wPrim_2 is Port ( iClk : in STD_LOGIC; --Rst : in STD_LOGIC; En : in STD_LOGIC; Addri : in STD_LOGIC_VECTOR (3 downto 0); Addro : in STD_LOGIC_VECTOR (3 downto 0); D : in STD_LOGIC_VECTOR (7 downto 0); Q : out STD_LOGIC_VECTOR (7 downto 0) ); end Reg16x8bit_wPrim_2; architecture Behavioral of Reg16x8bit_wPrim_2 is begin reg1bit_0 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(0), D => D(0), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_1 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(1), D => D(1), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_2 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(2), D => D(2), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_3 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(3), D => D(3), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_4 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(4), D => D(4), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_5 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(5), D => D(5), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_6 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(6), D => D(6), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); reg1bit_7 : RAM16X1D generic map (INIT => X"0000") port map (WCLK => iClk, WE => En, DPO => Q(7), D => D(7), A0 => Addri(0),A1 => Addri(1),A2 => Addri(2),A3 => Addri(3), DPRA0 => Addro(0),DPRA1 => Addro(1), DPRA2 => Addro(2),DPRA3 => Addro(3)); end Behavioral;