----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:57:00 10/11/2007 
-- Design Name: 
-- Module Name:    AutoRd - Behavioral 
-- Description:    A wrapper around getByte module for addressing 
--		   Ethernet Controller register RXAUTORD (0x01) specifically
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AutoRd is
   Port ( Clk : in  STD_LOGIC;
	  Rst : in  STD_LOGIC;
          Go : in  STD_LOGIC;
          Q : out  STD_LOGIC_VECTOR (7 downto 0);
          Done : out  STD_LOGIC;

          TxRx_Go : out  STD_LOGIC;
          TxRx_RiW : out  STD_LOGIC;
          TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
	  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
          TxRx_Done : in  STD_LOGIC
	);
end AutoRd;

architecture Behavioral of AutoRd is

	component getByte is
	    Port ( Clk : in  STD_LOGIC;
		   Rst : in  STD_LOGIC;
           	   Go : in  STD_LOGIC;
		   A : in STD_LOGIC_VECTOR (7 downto 0);
           	   Q : out  STD_LOGIC_VECTOR (7 downto 0);
           	   Done : out  STD_LOGIC;

           	   TxRx_Go : out  STD_LOGIC;
           	   TxRx_RiW : out  STD_LOGIC;
           	   TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
		   TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           	   TxRx_Done : in  STD_LOGIC 
		 );
	end component;
	
begin

	u1: getByte
	port map (Clk, Rst, Go, X"01", Q, Done, 
		  TxRx_Go, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

end Behavioral;