"C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 183: Unconnected output port 'db' of component 'INTCatcher'. "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 187: Unconnected output port 'TxRx_db' of component 'Transceiver'. "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 224: Unconnected output port 'db' of component 'Transmitter'. "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 232: Unconnected output port 'db' of component 'Idler_ctrl'. "C:/work/GlueX/Tagger/Electronics/FPGA/FPGA_ctrl.vhd" line 244: Unconnected output port 'db' of component 'Reader'. "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/EdgeCounter4bit.vhd" line 33: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <count1_sh> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 130: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Done_Hash2> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 262: Unconnected output port 'db' of component 'MACwrToAddr'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 268: Unconnected output port 'db' of component 'MACwrToAddr'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 272: Unconnected output port 'db' of component 'MACwrToAddr'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/Reset_hard.vhd" line 287: Unconnected output port 'db' of component 'MACwrToAddr'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 137: Unconnected output port 'db' of component 'MACwrToAddr'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 152: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Clk> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reset/MACaddrLoad.vhd" line 168: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Clk> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/Transmitter_ctrl.vhd" line 267: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Rst>, <Go_TxStart> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/MiscComp/RAwr2BtoAddr.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <RamAddr>, <D>, <Data> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Transmitter/S-Packet.vhd" line 95: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <PktNum>, <TempReg_Q>, <ADCReg_Q> "C:/work/GlueX/Tagger/Electronics/FPGA/MiscComp/Counter16bit.vhd" line 39: Width mismatch. <count> has a width of 16 bits but assigned expression is 20-bit wide. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 107: Unconnected output port 'ser_Go' of component 'GetTempVal'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 107: Unconnected output port 'ser_D' of component 'GetTempVal'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 107: Unconnected output port 'db' of component 'GetTempVal'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/Query_coord.vhd" line 149: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Rst> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Querier/GetADCval.vhd" line 64: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <En>, <cnt>, <Addr_Q> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Rst> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 95: Unconnected output port 'Done' of component 'wrToAddr'. "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 105: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <Clk> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Reader/Reader_ctrl.vhd" line 100: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <InitGo> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" line 93: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <InitGo> "C:/work/GlueX/Tagger/Electronics/FPGA/EthCtrl/Programmer/Programmer_ctrl.vhd" line 155: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <InitGo>, <DataStage> Signal <db_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_AlmostDone> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <En_Convo> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Found 1-bit latch for signal <RWflag>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Signal <Code_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Addr_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Output <Q<13:8>> is never assigned. Tied to value 000000. Output <db> is never assigned. Tied to value 0. Signal <Go_late> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <AddrL> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <En_sh> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <En_sh> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <Mask> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <ser_LogStr> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTval2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTval1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTname2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <INTname1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Go_INT2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_INT0_delayed> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT1<7:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT1<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT0<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT0<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Data_INT0<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Input <INT_Found<7:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <SPI_SDO2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <SPI_SDO1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Output <db> is never assigned. Tied to value 0. Input <DAC_Done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <i> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbtmp> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <VoltDataMSB<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <PermitNextByte> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_CPLenH> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <Rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <Wr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Signal <Done_Byte_late> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <TxRx_Q> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Output <db2> is never assigned. Tied to value 0. Signal <ser_Go_rc1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <WordCount> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go9> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go16> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <MACCfg<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <MACCfg<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Go_InitMAC> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_MACconfig> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_MACCF3> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_MACCF2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 1-bit latch for signal <db1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. Input <INT_Done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Input <INT_Found> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Output <INT_Go> is never assigned. Tied to value 0. Signal <wrMACaddrs_db> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_uSpack> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_uCheck2> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <ser_Go_uCheck1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <ser_Go_ACL2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_ACL> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_uCheck2> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_uCheck1> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_u0> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_ACL2> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <TxRx_Go_ACL> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <RAwrToAddr_db> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <RAwrGo_uTxLen> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <MACregs_A_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Len2B> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Go_TxD> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <Done_TxStatCheck> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_TxBufCheck> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Done_Len> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Data> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Output <db_serial> is never assigned. Signal <state_En_u3> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <state_En_u1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_u3> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go_Quer> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ser_Go> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <ser_D> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <dbtmp1> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <db_serial_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbInfoCnt_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbInfoCnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <dbInfo> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_u3> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_u1> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <TxRx_Go_Idl> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Transmitter_db> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <StateChCnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <SPI_SDI_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Reset_hard_db2> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Reset_hard_db1> is assigned but never used. This unconnected signal will be trimmed during the optimization process. Signal <Go_cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <GTS_PORT> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <GSR_PORT> is used but never assigned. This sourceless signal will be automatically connected to value 0. Signal <EthAccessCnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <DBbyte> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <DACtestAddr> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <DAC_iRst_int> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Signal <Cnt> is never used or assigned. This unconnected signal will be trimmed during the optimization process. Hierarchical block <u4> is unconnected in block <u10>. It will be removed from the design. Hierarchical block <u5> is unconnected in block <u10>. It will be removed from the design. The value init of the FF/Latch preDACstage hinder the constant cleaning in the block uDpack. You should achieve better results by setting this init to 0. The value init of the FF/Latch En hinder the constant cleaning in the block uDpack. You should achieve better results by setting this init to 0. FF/Latch <Data_4> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 1 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <uTxS2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 1 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 0 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <a1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_4> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_5> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_6> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_7> (without init value) has a constant value of 0 in block <uTxSt1>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_0> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_1> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_2> (without init value) has a constant value of 1 in block <u2>. This FF/Latch will be trimmed during the optimization process. FF/Latch <Data_3> (without init value) has a constant value of 0 in block <u2>. This FF/Latch will be trimmed during the optimization process. Node <Data_1> of sequential type is unconnected in block <r1>. Node <Data_2> of sequential type is unconnected in block <r1>. Node <Data_3> of sequential type is unconnected in block <r1>. Node <Data_4> of sequential type is unconnected in block <r1>. Node <Data_5> of sequential type is unconnected in block <r1>. Node <Data_6> of sequential type is unconnected in block <r1>. Node <Data_7> of sequential type is unconnected in block <r1>. Node <Data_2> of sequential type is unconnected in block <r2>. Node <Data_4> of sequential type is unconnected in block <r2>. Node <Data_5> of sequential type is unconnected in block <r2>. Node <Data_6> of sequential type is unconnected in block <r2>. Node <Data_7> of sequential type is unconnected in block <r2>. Node <Data_0> of sequential type is unconnected in block <m1a>. Node <Data_1> of sequential type is unconnected in block <m1a>. Node <Data_2> of sequential type is unconnected in block <m1a>. Node <Data_3> of sequential type is unconnected in block <m1a>. Node <Data_5> of sequential type is unconnected in block <m1a>. Node <Data_6> of sequential type is unconnected in block <m1a>. Node <Data_7> of sequential type is unconnected in block <m1a>. Node <Data_6> of sequential type is unconnected in block <r1>. Node <Data_7> of sequential type is unconnected in block <r1>. The value init of the FF/Latch preDACstage hinder the constant cleaning in the block DPacket. You should achieve better results by setting this init to 0. The value init of the FF/Latch En hinder the constant cleaning in the block DPacket. You should achieve better results by setting this init to 0. Node <uResH/db1> of sequential type is unconnected in block <FPGA_ctrl>. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q0<7>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q0<6>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q0<5>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q0<4>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q0<3>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q0<2>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q1<7>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q1<6>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q1<5>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q1<4>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q1<3>>; this signal is connected to multiple drivers. Multi-source in Unit <Reg32x14bit_wPrim> on signal <Q1<2>>; this signal is connected to multiple drivers.