There is a STARTUP component with a signal on the CLK pin but StartupClk is Cclk. Gated clock. Clock net DACregs_Rst is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net uXmit/uSpack/Done_Word is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net uXmit/uSpack/w/C_0_0_not0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net u0/Done_INT1 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.