----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:22:32 09/24/2007 
-- Design Name:    Multiplexed Registers for DAC voltage values
-- Module Name:    Reg16x8bit - Behavioral 
-- Description: 	 16 x 8bit muxed register bank 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Reg16x8bit is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addri : in  STD_LOGIC_VECTOR (3 downto 0);
           Addro : in  STD_LOGIC_VECTOR (3 downto 0);
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0));
end Reg16x8bit;

architecture Behavioral of Reg16x8bit is
	
	type register8bit is array (integer range <>) of STD_LOGIC_VECTOR (7 downto 0);
	signal reg : register8bit (15 downto 0);
	signal intAddri :  integer range 15 downto 0;
	signal intAddro :  integer range 15 downto 0;


begin

	intAddri <= conv_integer(Addri);
	intAddro <= conv_integer(Addro);

	Reg16x8bit : process (Clk, Rst, Wr, D, intAddri, Addri, intAddri, Addri)
	begin
	
		if (Rst = '1') then
--			for i in 7 downto 0 loop
--				reg(i) <= X"E7";
--			end loop;
			reg(0) <= X"00";
			reg(1) <= X"01";
			reg(2) <= X"02";
			reg(3) <= X"03";
			reg(4) <= X"04";
			reg(5) <= X"05";
			reg(6) <= X"06";
			reg(7) <= X"07";
			reg(8) <= X"08";
			reg(9) <= X"09";
			reg(10) <= X"0A";
			reg(11) <= X"0B";
			reg(12) <= X"0C";
			reg(13) <= X"0D";
			reg(14) <= X"0E";
			reg(15) <= X"0F";

		else
			if falling_edge(Clk) then
				if (Wr = '1') then
					reg(intAddri) <= D;
				else reg <= reg;
				end if;
			else reg <= reg;
			end if;
		end if;
	end process Reg16x8bit;

	Q <= reg(intAddro);

end Behavioral;