----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:22:32 09/24/2007 
-- Design Name:    Multiplexed Registers for DAC voltage values
-- Module Name:    Reg128x8bit - Behavioral 
-- Description: 	 128 x 8bit muxed register bank 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Reg128x8bit is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addri : in  STD_LOGIC_VECTOR (6 downto 0);
           Addro : in  STD_LOGIC_VECTOR (6 downto 0);
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0));
end Reg128x8bit;

architecture Behavioral of Reg128x8bit is
	
	type register8bit is array (integer range <>) of STD_LOGIC_VECTOR (7 downto 0);
	signal reg : register8bit (127 downto 0);
	signal intAddri :  integer range 127 downto 0;
	signal intAddro :  integer range 127 downto 0;


begin

	intAddri <= conv_integer(Addri);
	intAddro <= conv_integer(Addro);

	proc : process (Clk, Rst, Wr, D, intAddri, Addri, intAddri, Addri)
	begin
	
		if (Rst = '1') then
			for i in 127 downto 0 loop
				reg(i) <= X"E7";
			end loop;

		else
			if falling_edge(Clk) then
				if (Wr = '1') then
					reg(intAddri) <= D;
				else reg <= reg;
				end if;
			else reg <= reg;
			end if;
		end if;
	end process proc;

	Q <= reg(intAddro);

end Behavioral;