----------------------------------------------------------------------------------
-- Company:   University of Connecticut
-- Engineer:  Igor Senderovich
-- 
-- Create Date:    09:40:38 11/12/2007 
-- Design Name: 
-- Module Name:    Counter24bit - Behavioral 
-- Description:    24-bit counter that measures out 2^16 cycles and reports "Done"
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter24bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
end Counter24bit;

architecture Behavioral of Counter24bit is

	signal count : STD_LOGIC_VECTOR (23 downto 0);
	signal Go_sh : STD_LOGIC;
begin
		
	Counter24bit : process (Clk, Go, Rst)
	begin
		if (Rst='1') then
			count <= X"000000";
		else
			if falling_edge(Clk) then
				Go_sh <= Go;
			end if;
			
			if rising_edge(Clk) then
				if (count=X"000000") then
					count <= count + (X"0000" & "0000000" & Go_sh);
				else
					count <= count + X"000001";
				end if;
			else
				count <= count;
			end if;
		end if;
	end process;
	
	Done <= '1' when (count=X"FFFFFF") else '0';
end Behavioral;