----------------------------------------------------------------------------------
-- Company:   University of Connecticut
-- Engineer:  Igor Senderovich
-- 
-- Create Date:    09:40:38 11/12/2007 
-- Design Name: 
-- Module Name:    Counter21bit - Behavioral 
-- Description:    21-bit counter that measures out 2^16 cycles and reports "Done"
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Counter21bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
end Counter21bit;

architecture Behavioral of Counter21bit is

	signal count : STD_LOGIC_VECTOR (20 downto 0);
	signal Go_sh : STD_LOGIC;
begin
		
	Counter21bit : process (Clk, Go, Rst)
	begin
		if (Rst='1') then
			count <= "000000000000000000000";
		else
			if falling_edge(Clk) then
				Go_sh <= Go;
			end if;

			if rising_edge(Clk) then
				if (count="000000000000000000000") then
					count <= count + (X"00000" & Go_sh);
				else
					count <= count + X"000000000000000000001";
				end if;
			else
				count <= count;
			end if;
		end if;
	end process;
	
	Done <= '1' when (count="111111111111111111111") else '0';
end Behavioral;