----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:57:51 08/07/2009 
-- Design Name: 
-- Module Name:    Includes - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package MainComp is

	component stateReg is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in  STD_LOGIC;
           En : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (2 downto 0);
           Q : out  STD_LOGIC_VECTOR (2 downto 0));
	end component;
	component MACregs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (3 downto 0);
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;
	component TempReg is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (9 downto 0);
           Q : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;
	component ADCregs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (2 downto 0);
           D : in  STD_LOGIC_VECTOR (11 downto 0);
           Q : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;
	component DACregs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (4 downto 0);
           D : in  STD_LOGIC_VECTOR (13 downto 0);
           Q : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;

	component Reset_hard is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
			  Eth_iRst : inout STD_LOGIC;
			  
			  state_En : out STD_LOGIC;
			  state_D  : out STD_LOGIC_VECTOR (2 downto 0);
			  state_Q : in STD_LOGIC_VECTOR (2 downto 0);

			  MACregs_En : out STD_LOGIC;
			  MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
			  MACregs_D  : out STD_LOGIC_VECTOR (7 downto 0);
			  
			  --Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
			  TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Done : in  STD_LOGIC;
			  
			  --Interrupt catcher control lines
			  INT_Go		: out STD_LOGIC;
			  INT_Mask	: out STD_LOGIC_VECTOR (7 downto 0);
			  INT_Found	: in STD_LOGIC_VECTOR (7 downto 0);
			  INT_Done	: in STD_LOGIC;

			  dbShort : in STD_LOGIC;
 			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
 
			  db1 : out STD_LOGIC;
			  db2 : out STD_LOGIC
			  );
	end component;
	component Reset_soft is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           DAC_iRST : out  STD_LOGIC;
           --ADC_Rst : out  STD_LOGIC;
			  
			  state_En : out STD_LOGIC;
			  state_D  : out STD_LOGIC_VECTOR (2 downto 0);
			  state_Q : in STD_LOGIC_VECTOR (2 downto 0);
			  
			  MACregs_En : out STD_LOGIC;
			  MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
			  MACregs_D  : out STD_LOGIC_VECTOR (7 downto 0);

			  DBbyte	: out STD_LOGIC_VECTOR (7 downto 0);

			  --Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
			  TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Done : in  STD_LOGIC;
			  
			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0)
			);
	end component;

	component Transceiver is
    Port ( fClk : in  STD_LOGIC; -- "fast" clock of the EthCtrl
			  sClk : out  STD_LOGIC; -- "slow" clock for the FPGA
			  Rst : in STD_LOGIC;
			-- MuxIntel lines ------------------------
			  ALE : out STD_LOGIC;
			  AD  : inout STD_LOGIC_VECTOR (7 downto 0);
			  iRD : out STD_LOGIC;
			  iWR : out STD_LOGIC;
			-- FPGA-Internal input lines -------------
           TxRx_Go : in  STD_LOGIC;
           TxRx_RiW : in  STD_LOGIC;
           TxRx_A : in  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : in  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : out STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : out  STD_LOGIC;
  			  TxRx_db : out STD_LOGIC
			  );
	end component;
	
	component Transmitter is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

			  LocStamp : in STD_LOGIC_VECTOR (7 downto 0);
			  --PktNum : in STD_LOGIC_VECTOR (15 downto 0);

			  MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
			  MACregs_Q  : in STD_LOGIC_VECTOR (7 downto 0);

			  TempReg_Q : in STD_LOGIC_VECTOR (15 downto 0);
			  ADCReg_Addr : out  STD_LOGIC_VECTOR (2 downto 0);
           ADCReg_Q : in  STD_LOGIC_VECTOR (15 downto 0);
			  DACReg_Addr : out  STD_LOGIC_VECTOR (4 downto 0);
           DACReg_Q : in  STD_LOGIC_VECTOR (15 downto 0);

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;
			  
			  --Interrupt catcher control lines
			  INT_Go		: out STD_LOGIC;
			  INT_Mask	: out STD_LOGIC_VECTOR (7 downto 0);
			  INT_Found	: in STD_LOGIC_VECTOR (7 downto 0);
			  INT_Done	: in STD_LOGIC;

 			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
			  db : out STD_LOGIC
			);
	end component;
	
	component Idler_ctrl is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

			  --Interrupt catcher control lines
			  INT_Go		: out STD_LOGIC;
			  INT_Mask	: out STD_LOGIC_VECTOR (7 downto 0);
			  INT_Found	: in STD_LOGIC_VECTOR (7 downto 0);
			  INT_Done	: in STD_LOGIC;
			  
			  db : out STD_LOGIC);
	end component;
	component Reader is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

			  LocStamp : in STD_LOGIC_VECTOR (7 downto 0);

			  --Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
			  TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Done : in  STD_LOGIC;
			  
			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
			  db : out STD_LOGIC
     );
	end component;
	component Querier is
	Port (Clk : in  STD_LOGIC;
			Rst : in  STD_LOGIC;

		-- SPI bus (with ADC and Temp sensors) lines
			SPI_SCLK 	: out STD_LOGIC;
			SPI_T_CE	: out STD_LOGIC;
			SPI_A_iCS	: out STD_LOGIC;
			SPI_SDI	: out STD_LOGIC;
			SPI_SDO	: in STD_LOGIC;

		-- Regusters
			ADCreg_En : out  STD_LOGIC;
			ADCreg_A  : out STD_LOGIC_VECTOR (2 downto 0);
			ADCreg_D  : out STD_LOGIC_VECTOR (11 downto 0);
			Tempreg_En : out STD_LOGIC;
			Tempreg_D : out  STD_LOGIC_VECTOR (9 downto 0);
		
		-- state bus
			stateEn : out STD_LOGIC;
			stateD : out  STD_LOGIC_VECTOR (2 downto 0);
			stateQ : in STD_LOGIC_VECTOR (2 downto 0);		

			ser_Go : out STD_LOGIC;
			ser_D : out STD_LOGIC_VECTOR (7 downto 0);
			db : out STD_LOGIC);		  		  
	end component;
--	component SPIctrl is
--    Port ( ---- Input ----
--			  Clk : in  STD_LOGIC;
--           iRst_in : in  STD_LOGIC;
--           T_iA : in  STD_LOGIC;
--           Go : in  STD_LOGIC;
--           Addr : in  STD_LOGIC_VECTOR (2 downto 0);
--           SDO : in  STD_LOGIC;
--			  ---- Output ----
--           SCLK : out  STD_LOGIC;
--           iRst_out : out  STD_LOGIC;
--           SDI : out  STD_LOGIC;
--           T_CE : out  STD_LOGIC;
--           A_iCS : out  STD_LOGIC;
--           Done : out  STD_LOGIC;
--           T_Q : out  STD_LOGIC_VECTOR (9 downto 0);
--           A_A : out  STD_LOGIC_VECTOR (2 downto 0);
--           A_Q : out  STD_LOGIC_VECTOR (11 downto 0);
--			  
--			  ser_Go : out STD_LOGIC;
--			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
--			  db : out STD_LOGIC
--			  );
--	end component;
	component Programmer_ctrl is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;

           DAC_iGo : out  STD_LOGIC;
           DACReg_En : out  STD_LOGIC;
           DAC_Addr : out  STD_LOGIC_VECTOR (4 downto 0);
           DAC_D : out  STD_LOGIC_VECTOR (13 downto 0);
			  DAC_Done : in STD_LOGIC;
			  DAC_Qmax : in STD_LOGIC_VECTOR (13 downto 0);

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_D : out STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;
			  
			  db1 : out STD_LOGIC;
			  db2 : out STD_LOGIC
		);
	end component;
	component DAC_controller
		Port	(	CLK			: in  STD_LOGIC;
					invRst		: in  STD_LOGIC;
					--invDRst_in	: in  STD_LOGIC;
					invTxGo		: in  STD_LOGIC;
					Addr			: in  STD_LOGIC_VECTOR (4 downto 0);
					Code			: in  STD_LOGIC_VECTOR (13 downto 0);
					--SCLK			: out  STD_LOGIC;
					invSYNC		: out  STD_LOGIC;
					Data 			: out  STD_LOGIC;
					--invDRst_out : out  STD_LOGIC;
					Done : out STD_LOGIC);
	end component;
	
	component INTCatcher is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
			  Eth_iINT: in STD_LOGIC;
           Go : in  STD_LOGIC;
           Mask : in  STD_LOGIC_VECTOR(7 downto 0); --INT flag mask
			  INTs : out  STD_LOGIC_VECTOR(7 downto 0);
			  Done : out STD_LOGIC;
			  
			  --Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC := 'Z';
			  TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Done : in  STD_LOGIC;
			  
 			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);

			  db : out STD_LOGIC);
	end component;

end package;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

package BasicComp is
	
	constant dbSTRLEN : integer := 30;

	component Reg8bit is
		Port(Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           En : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;
	
	component EdgeCounter4bit is
		Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go : in  STD_LOGIC;
			  En : out STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (3 downto 0));
	end component;
	
	component Counter4bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
	end component;

	component StepCounter8bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
			  Q   : out STD_LOGIC_VECTOR (7 downto 0));
	end component;
	component StepCounter16bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
			  Q   : out STD_LOGIC_VECTOR (15 downto 0));
	end component;

	component Counter24bit is -- ~3.4s @ 5MHz
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
	end component;
	
	component Counter21bit is -- ~420ms @ 5MHz
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
	end component;

	component Counter16bit is -- ~13ms @ 5MHz
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
	end component;

	component Counter12bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
           Done : out  STD_LOGIC);
	end component;
	
	component Counter7bit is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go  : in  STD_LOGIC;
			  En  : out STD_LOGIC;
           Done : out  STD_LOGIC);
	end component;

	component c_delay is
		Port ( Clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
	end component;
	component c_dbldelay is
		Port ( Clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
	end component;

	component pulser is
		Port ( Clk : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
	end component;
	component pulser_db is
    Port ( Clk : in  STD_LOGIC;
			  D   : in  STD_LOGIC;
           Q   : out  STD_LOGIC;
           Qa_db : out  STD_LOGIC;
           Qb_db : out  STD_LOGIC);
	end component;
	component Pulse_Delay is
		 Port ( Clk : in STD_LOGIC;
				  D   : in STD_LOGIC;
				  Q   : out STD_LOGIC);
	end component;

	component wr2BtoAddr is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
			  Go : in STD_LOGIC;
			  A : in STD_LOGIC_VECTOR (7 downto 0); 
			  D : in STD_LOGIC_VECTOR (15 downto 0);        -- Data
           TxRx_Go : out  STD_LOGIC;   -- Transceiver command lines
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC := 'Z';
           TxRx_Done : in  STD_LOGIC;
			  Done : out STD_LOGIC
			  );
	end component;
	
	component wrToAddr is
    Port ( Clk : in  STD_LOGIC;
			  Rst : STD_LOGIC;
			  Go : in STD_LOGIC;                      -- pulse to start
			  A : in STD_LOGIC_VECTOR (7 downto 0);   -- address
			  D : in STD_LOGIC_VECTOR (7 downto 0);   -- data to be written
           -- Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC := 'Z';
			  TxRx_Done : in  STD_LOGIC;

			  Done : out STD_LOGIC -- signal of end of write (=TxRx_Done)
			  );
	end component;

	component InspectReg is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go : in STD_LOGIC;
			  Addr : in STD_LOGIC_VECTOR (7 downto 0);
			  Done : out STD_LOGIC;
			  
			-- Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;

			-- Serial log output lines
 			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
			  db : out STD_LOGIC
			);
	end component;

	component AutoRd is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (7 downto 0);
           Done : out  STD_LOGIC;

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC );
	end component;
	
	component getByte is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
			  A : in STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0);
           Done : out  STD_LOGIC;

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC );
	end component;
	component getByte_db is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
			  A : in STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0);
           Done : out  STD_LOGIC;

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_Aout : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Din : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;
			  db : out STD_LOGIC);
	end component;
	
	
	component MACwrToAddr is
    Port ( Clk : in  STD_LOGIC;
			  Rst : STD_LOGIC;
			  Go : in STD_LOGIC;                      -- pulse to start
			  A : in STD_LOGIC_VECTOR (7 downto 0);   -- address
			  D : in STD_LOGIC_VECTOR (15 downto 0);  -- data to be written
           -- Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
			  TxRx_Done : in  STD_LOGIC;

			  Done : out STD_LOGIC;
			  db : out STD_LOGIC
			  );
	end component;
	

	component SerStringOut is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
			  Go : in STD_LOGIC;
           D : in  STRING (1 to dbSTRLEN);
			  Q : out STD_LOGIC;
			  Done : out STD_LOGIC;
			  db1 : out STD_LOGIC;
			  db2 : out STD_LOGIC
			  );
	end component;
	component SerialOut is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
			  En : in STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC;
			  Done : out STD_LOGIC;
			  db : out STD_LOGIC);
	end component;
	
	component SerialOutFIFO is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
			  Go  : in STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC;
			  --Done : out STD_LOGIC;
			  db : out STD_LOGIC
			  );
	end component;


	component Trigger is
    Port ( Rst : STD_LOGIC;
			  Arm  : in STD_LOGIC;
			  Sig  : in STD_LOGIC;
			  Trig : out STD_LOGIC);
	end component;

	component DropOnSig is
		 Port ( Rst : STD_LOGIC;
				  D : in STD_LOGIC;
				  Q : out STD_LOGIC);
	end component;

	component CountEvents is
    Port ( Clk : in STD_LOGIC;
			  Rst : in STD_LOGIC;
			  D : in STD_LOGIC;
			  Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 : out STD_LOGIC);
	end component;


end package;

----------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use BasicComp.all;

entity Pulse_Delay is
    Port ( Clk : in STD_LOGIC;
			  D   : in STD_LOGIC;
			  Q   : out STD_LOGIC);
end Pulse_Delay;

architecture Behavioral of Pulse_Delay is
	signal R : STD_LOGIC;		
begin

	u1: pulser port map (Clk, D, R);
	u2: c_delay port map (Clk, R, Q);
		
end Behavioral;




--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Trigger is
    Port ( Rst : STD_LOGIC;
			  Arm  : in STD_LOGIC;
			  Sig  : in STD_LOGIC;
			  Trig : out STD_LOGIC);
end Trigger;

architecture Behavioral of Trigger is

	signal waiting : std_LOGIC;
				
begin

	Prep : process (Rst, Arm, Sig) begin
		if Rst='1' then waiting <= '0';
		else
			if Arm='1' then
				waiting <= '1';
			else
				if falling_edge(Sig) then
					waiting <= '0';
				end if;
			end if;
		end if;
	end process;
	Trig <= Sig and waiting;
	
end Behavioral;



------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DropOnSig is
    Port ( Rst : in STD_LOGIC;
			  D : in STD_LOGIC;
			  Q : out STD_LOGIC);
end DropOnSig;

architecture Behavioral of DropOnSig is
begin

	proc : process (Rst, D)
	begin
		if Rst='1' then Q <= '1';
		else
			if D = '1' then
				Q <= '0';
			end if;
		end if;
	end process;
	
end Behavioral;

------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use FPGA_BasicComp.BasicComp.all;

entity CountEvents is
    Port ( Clk : in STD_LOGIC;
			  Rst : in STD_LOGIC;
			  D : in STD_LOGIC;
			  Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7 : out STD_LOGIC);
end CountEvents;

architecture Behavioral of CountEvents is

	signal cnt : STD_LOGIC_VECTOR (7 downto 0);
	signal Go : STD_LOGIC;

begin
	u1: pulser port map (Clk, D, Go);

	proc : process (Clk, Rst, Go)
	begin
		if Rst='1' then cnt <= X"00";
		else
			if falling_edge(Clk) and Go='1' then
				cnt <= cnt + "00000001";
			end if;
		end if;
	end process;
	
	Q0 <= cnt(0);	Q1 <= cnt(1);
	Q2 <= cnt(2);	Q3 <= cnt(3);
	Q4 <= cnt(4);	Q5 <= cnt(5);
	Q6 <= cnt(6);	Q7 <= cnt(7);
	
end Behavioral;